External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide
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- 4.1.2. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component
- 4.3.2. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component
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7.3.1.3. Maximum Number of Interfaces
Unless otherwise noted, the calculation for the maximum number of interfaces is based on independent interfaces where the address or command pins are not shared.
Device | Package | Component Interface | DIMM Interface |
---|---|---|---|
AGMA032 / AGMA039 / AGMB032 / AGMB039 | R31B | 7 - x16 5 - 2ch x16 7 - x16 + ECC 7 - x32 5 - x32 + ECC |
3 - 2ch x32 1 - 2ch x32 + ECC |
AGME032 / AGME039 / AGMF032 / AGMF039 / AGMG032 / AGMG039 / AGMH032 / AGMH039 | R47A | 8 | 4 |
AGMF032 / AGMF039 / AGMH032 / AGMH039 | R47B | 8 | 4 |
- Component Interface refers to 2ch x16, x16, x16 + ECC, x32 and x32+ ECC which can be implemented within a single IO96B bank.
- One DIMM interface requires two adjacent IO96B banks located on the edge of the device.
Timing closure depends on device resource and routing utilization. For more information about timing closure, refer to the Area and Timing Optimization Techniques chapter in the Quartus® Prime Handbook.