External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 3/31/2025
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7.3.1.3. Maximum Number of Interfaces

The maximum number of interfaces supported for a given memory protocol varies, depending on the FPGA in use.

Unless otherwise noted, the calculation for the maximum number of interfaces is based on independent interfaces where the address or command pins are not shared.

Note: You may need to share PLL clock outputs depending on your clock network usage.
Table 190.  Maximum Number of DDR5 Interfaces
Device Package Component Interface DIMM Interface
AGMA032 / AGMA039 / AGMB032 / AGMB039 R31B

7 - x16

5 - 2ch x16

7 - x16 + ECC

7 - x32

5 - x32 + ECC

3 - 2ch x32

1 - 2ch x32 + ECC

AGME032 / AGME039 / AGMF032 / AGMF039 / AGMG032 / AGMG039 / AGMH032 / AGMH039 R47A 8 4
AGMF032 / AGMF039 / AGMH032 / AGMH039 R47B 8 4
  • Component Interface refers to 2ch x16, x16, x16 + ECC, x32 and x32+ ECC which can be implemented within a single IO96B bank.
  • One DIMM interface requires two adjacent IO96B banks located on the edge of the device.

Timing closure depends on device resource and routing utilization. For more information about timing closure, refer to the Area and Timing Optimization Techniques chapter in the Quartus® Prime Handbook.