Parameterizable Macros for Intel FPGAs User Guide

Download PDF
ID 772350
Date 4/17/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the Parameterizable Macros for Intel FPGAs User Guide 2. List of Parameterizable Macros for Intel FPGAs 3. Inserting HDL Code from Parameterizable Macros Template 4. Dual-Port Random Access Memory (RAM) 5. FIFO 6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
4. Dual-Port Random Access Memory (RAM) x
4.1. Simple Dual-Port RAM 4.2. True Dual-Port RAM
4.1. Simple Dual-Port RAM x
4.1.1. Port Descriptions 4.1.2. Parameters 4.1.3. Instantiation Template
4.2. True Dual-Port RAM x
4.2.1. Port Description 4.2.2. Parameters 4.2.3. Instantiation Template
5. FIFO x
5.1. Asynchronous FIFO (async_fifo/ASYNC_FIFO) 5.2. Synchronous FIFO (sync_fifo/SYNC_FIFO)
5.1. Asynchronous FIFO (async_fifo/ASYNC_FIFO) x
5.1.1. Port Descriptions 5.1.2. Parameters 5.1.3. Instantiation Template
5.2. Synchronous FIFO (sync_fifo/SYNC_FIFO) x
5.2.1. Port Descriptions 5.2.2. Parameters 5.2.3. Instantiation Template
1. About the Parameterizable Macros for Intel FPGAs User Guide
2. List of Parameterizable Macros for Intel FPGAs
3. Inserting HDL Code from Parameterizable Macros Template
4. Dual-Port Random Access Memory (RAM)
5. FIFO
6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide

5.1.1. Port Descriptions

Table 5.  ASYNC_FIFO Parameterizable Macros Port Descriptions
Port Type Required Description
wrclk Input Yes Positive-edge-triggered clock.

Use to synchronize the following ports:

  • data
  • wrreq
  • wrfull
  • wrempty
  • wrusedw
rdclk Input Yes Positive-edge-triggered clock.

Use to synchronize the following ports:

  • q
  • rdreq
  • rdfull
  • rdempty
  • rdusedw
data Input Yes Holds the data to be written in the FIFO when the wrreq signal is asserted. The port width is equal to the DATA_WIDTH parameter.
wrreq Input Yes Assert this signal to request for a write operation.

Ensure that the following conditions are met:

  • Do not assert the wrreq signal when the wrfull port is high. Enable the overflow protection circuitry or set the OVERFLOW_CHECKING parameter to ON so that the FIFO can automatically disable the wrreq signal when it is full.
  • The wrreq signal must meet the functional timing requirement based on the full or wrfull signal.
  • Do not assert the wrreq signal during the deassertion of the aclr signal. Violating this requirement creates a race condition between the falling edge of the aclr signal and the rising edge of the write clock if the wrreq port is set to high.
  • Set the WRITE_ACLR_SYNCH parameter to ON to synchronize the aclr signal with the wrclk clock.
rdreq Input Yes Assert this signal to request for a read operation. The rdreq signal acts differently in normal mode and show-ahead mode.

Ensure that the following conditions are met:

  • Do not assert the rdreq signal when the rdempty port is high. Enable the underflow protection circuitry or set the UNDERFLOW_CHECKING parameter to ON so that the FIFO can automatically disable the rdreq signal when it is empty.
  • The rdreq signal must meet the functional timing requirement based on the rdempty signal.
aclr Input No Assert this signal to clear all the output status ports, but the effect on the q output may vary for different FIFO configurations.
q Output Yes

Shows the data read from the read request operation.

The width of the q port must be equal to the width of the data port. The port width is equal to the DATA_WIDTH_A parameter. For the mixed width FIFO, the width of the q port can be different from the width of the data port. You need to ensure the width of the q port is equal to the DATA_WIDTH_B parameter. The FIFO macro supports a wide write port with a narrow read port, and vice versa. However, the width ratio is restricted by the type of RAM block, and in the power of 2.

wrfull

rdfull

Output No

When asserted, the FIFO is considered full. Do not perform write request operation when the FIFO is full.

The rdfull signal functions as a combinational output instead of a derived version of the wrfull signal. Therefore, you must always refer to the wrfull port to ensure whether or not a valid write request operation can be performed, regardless of the target device.

wrempty

rdempty

Output No

When asserted, the FIFO is considered empty. Do not perform read request operation when the FIFO is empty.

The wrempty signal functions as a combinational output instead of a derived version of the rdempty signal. Therefore, you must always refer to the rdempty port to ensure whether or not a valid read request operation can be performed, regardless of the target device.

wrusedw

rdusedw

Output No Show the number of words stored in the FIFO.

Ensure that the wrusedw port width is equal to the ADDR_WIDTH_A parameter, and the rdusedw port width is equal to the ADDR_WIDTH_B parameter. For the ASYNC_FIFO_MIXED_WIDTH function, the width of the wrusedw and rdusedw ports must be equal to the ADDR_WIDTH_A and ADDR_WIDTH_B parameters respectively.

The FIFO shows full even before the number of words stored reaches its maximum value. Therefore, you must always refer to the wrfull port for valid write request operation, and the rdempty port for valid read request operation regardless of the target device.

byteena Input Yes

Byte enable port at Port A to masks the data_a port so that only specific bits of data are written to the memory.

This port is enabled in FIFO because the pseudo RAM supports data with byte_size.

Level Two Title