Parameterizable Macros for Intel FPGAs User Guide

Download PDF
ID 772350
Date 4/17/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the Parameterizable Macros for Intel FPGAs User Guide 2. List of Parameterizable Macros for Intel FPGAs 3. Inserting HDL Code from Parameterizable Macros Template 4. Dual-Port Random Access Memory (RAM) 5. FIFO 6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
4. Dual-Port Random Access Memory (RAM) x
4.1. Simple Dual-Port RAM 4.2. True Dual-Port RAM
4.1. Simple Dual-Port RAM x
4.1.1. Port Descriptions 4.1.2. Parameters 4.1.3. Instantiation Template
4.2. True Dual-Port RAM x
4.2.1. Port Description 4.2.2. Parameters 4.2.3. Instantiation Template
5. FIFO x
5.1. Asynchronous FIFO (async_fifo/ASYNC_FIFO) 5.2. Synchronous FIFO (sync_fifo/SYNC_FIFO)
5.1. Asynchronous FIFO (async_fifo/ASYNC_FIFO) x
5.1.1. Port Descriptions 5.1.2. Parameters 5.1.3. Instantiation Template
5.2. Synchronous FIFO (sync_fifo/SYNC_FIFO) x
5.2.1. Port Descriptions 5.2.2. Parameters 5.2.3. Instantiation Template
1. About the Parameterizable Macros for Intel FPGAs User Guide
2. List of Parameterizable Macros for Intel FPGAs
3. Inserting HDL Code from Parameterizable Macros Template
4. Dual-Port Random Access Memory (RAM)
5. FIFO
6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide

4.1.2. Parameters

Table 2.  Simple Dual-Port RAM Parameterizable Macros Parameters
Name Allowed Values Description
ADDR_REG_B_ACLR

NONE

CLEAR0

Clear for read address registers at Port B.
ADDR_REG_B_CLK

CLOCK1

CLOCK0

Clock choice for address registers at Port B.
ADDR_WIDTH_A 11 Address width of Port A.
ADDR_WIDTH_B 11 Address width of Port B.
RDCONTROL_REG_B

CLOCK1

CLOCK0

Clock choice for read control registers at Port B.
BYTEENA_REG_B

CLOCK1

CLOCK0

Clock for byte enable registers at Port B.
BYTE_EN_WIDTH_A 1 Width of the byte enable bus at Port A. The width for BYTE_EN_WIDTH_A should be equal to DATA_WIDTH_A divided by BYTE_SIZE.
BYTE_SIZE

5

8

9

10

Specifies the size of the byte for byte-enable mode.
DATA_REG_B_ACLR

CLEAR1

CLEAR0

NONE

Asynchronous clear for data output registers at Port B. When DATA_REG_B_CLK is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch.
DATA_REG_B_CLK

UNREGISTERED

CLOCK1

CLOCK0

Clock choice for data output registers at Port B.
DATA_REG_B_SCLR

NONE

SCLEAR

Synchronous clear for data output registers at Port B. When DATA_REG_B_CLK is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch.
DATA_WIDTH_A 8 Data width of Port A.
DATA_WIDTH_B 8 Data width of Port B.
ENABLE_COHERENT_READ

TRUE

FALSE

Enables or disables the coherent read feature.
ENABLE_FORCE_TO_ZERO

TRUE

FALSE

Enables or disables the Force-to-Zero feature.

Force-to-Zero feature can help to improve the performance of glue logic when the memory depth is larger than a single memory block.

INIT_FILE

*.mif

*.hex

Specifies the initialization file.
INIT_FILE_LAYOUT

PORT_A

PORT_B 		Specifies the layout of the initialization file.
IN_CLOCK_EN_A

NORMAL

BYPASS

Specifies the clock enable being used for the input registers of Port A.
IN_CLOCK_EN_B

NORMAL

BYPASS

Specifies the clock enable being used for the input registers of Port B.
MAX_DEPTH 2048 Specifies the depth of the RAM slices.
OUT_CLOCK_EN_B

NORMAL

BYPASS

Specifies the clock enable being used for the output registers of Port B.
RAM_BLOCK_TYPE

Auto

M20K

Specifies the RAM block type.
READ_DURING_WRITE_MODE_MIXED_PORTS

DONT_CARE

NEW_DATA

OLD_DATA

The behavior of read-during-write mode in mixed-ports.

  • The value of NEW_DATA is supported only when the read address and output data are registered by the write clock in the MLAB mode.
  • The value of DONT_CARE is supported only in the MLAB mode.
Level Two Title