Parameterizable Macros for Intel FPGAs User Guide

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ID 772350
Date 4/17/2023
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Document Table of Contents
Document Table of Contents x
1. About the Parameterizable Macros for Intel FPGAs User Guide 2. List of Parameterizable Macros for Intel FPGAs 3. Inserting HDL Code from Parameterizable Macros Template 4. Dual-Port Random Access Memory (RAM) 5. FIFO 6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
4. Dual-Port Random Access Memory (RAM) x
4.1. Simple Dual-Port RAM 4.2. True Dual-Port RAM
4.1. Simple Dual-Port RAM x
4.1.1. Port Descriptions 4.1.2. Parameters 4.1.3. Instantiation Template
4.2. True Dual-Port RAM x
4.2.1. Port Description 4.2.2. Parameters 4.2.3. Instantiation Template
5. FIFO x
5.1. Asynchronous FIFO (async_fifo/ASYNC_FIFO) 5.2. Synchronous FIFO (sync_fifo/SYNC_FIFO)
5.1. Asynchronous FIFO (async_fifo/ASYNC_FIFO) x
5.1.1. Port Descriptions 5.1.2. Parameters 5.1.3. Instantiation Template
5.2. Synchronous FIFO (sync_fifo/SYNC_FIFO) x
5.2.1. Port Descriptions 5.2.2. Parameters 5.2.3. Instantiation Template
1. About the Parameterizable Macros for Intel FPGAs User Guide
2. List of Parameterizable Macros for Intel FPGAs
3. Inserting HDL Code from Parameterizable Macros Template
4. Dual-Port Random Access Memory (RAM)
5. FIFO
6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide

5.2.1. Port Descriptions

Table 7.  SYNC_FIFO Parameterizable Macros Port Descriptions
Port Type Required Description
clock Input Yes Positive-edge-triggered clock.
data Input Yes Holds the data to be written in the FIFO when the wrreq signal is asserted. The port width is equal to the DATA_WIDTH parameter.
wrreq Input Yes Assert this signal to request for a write operation.

Ensure that the following conditions are met:

  • Do not assert the wrreq signal when the full port is high. Enable the overflow protection circuitry or set the OVERFLOW_CHECKING parameter to ON so that the FIFO can automatically disable the wrreq signal when it is full.
  • The wrreq signal must meet the functional timing requirement based on the full signal.
  • Do not assert the wrreq signal during the deassertion of the aclr signal. Violating this requirement creates a race condition between the falling edge of the aclr signal and the rising edge of the write clock if the wrreq port is set to high.
rdreq Input Yes Assert this signal to request for a read operation. The rdreq signal acts differently in normal mode and show-ahead mode.

Ensure that the following conditions are met:

  • Do not assert the rdreq signal when the empty port is high. Enable the underflow protection circuitry or set the UNDERFLOW_CHECKING parameter to ON so that the FIFO can automatically disable the rdreq signal when it is empty.
  • The rdreq signal must meet the functional timing requirement based on the empty signal.
sclr/aclr Input No Assert this signal to clear all the output status ports, but the effect on the q output may vary for different FIFO configurations.
q Output Yes Shows the data read from the read request operation.

The width of the q port must be equal to the width of the data port. The port width is equal to the DATA_WIDTH parameter.

full

Output No

When asserted, the FIFO is considered full. Do not perform write request operation when the FIFO is full.

empty

Output No

When asserted, the FIFO is considered empty. Do not perform read request operation when the FIFO is empty.
almost_full Output No

Asserted when the usedw signal is greater than or equal to the ALMOST_FULL_VALUE parameter. It is used as an early indication of the full signal.

almost_empty Output No

Asserted when the usedw signal is lesser than the ALMOST_EMPTY_VALUE parameter. It is used as an early indication of the empty signal.

usedw

Output No Show the number of words stored in the FIFO.

Port width must be equal to the ADDR_WIDTH parameter.

byteena Input Yes

Byte enable port at Port A to masks the data_a port so that only specific bits of data are written to the memory.

This port is enabled in FIFO because the simple RAM supports data with BYTE_SIZE.

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