Parameterizable Macros for Intel FPGAs User Guide

ID 772350
Date 4/17/2023

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The FIFO functions are mostly applied in data buffering applications that comply with the first-in-first-out data flow in synchronous or asynchronous clock domains. SYNC_FIFO/sync_fifo is a synchronous FIFO and uses the same clock signal to perform the read and write operations. ASYNC_FIFO/async_fifo is an asynchronous FIFO and uses the rdclk or wrclk signal to perform the read or write operation, respectively.

The parameterizable SYNC_FIFO/sync_fifo and ASYNC_FIFO/async_fifo modules can be instantiated using the instantiation templates available in Intel® Quartus® Prime Pro Edition, starting from version 23.1. The SYNC_FIFO/sync_fifo module can be instantiated using the synchronous FIFO template (sync_fifo or SYNC_FIFO), while the ASYNC_FIFO/async_fifo module can be instantiated using the asynchronous FIFO template (async_fifo or ASYNC_FIFO).

This section provides the block diagrams, port descriptions, parameter tables, and instantiation templates of the SYNC_FIFO/sync_fifo and ASYNC_FIFO/async_fifo macro modules. For more information on these FIFO modules, such as the timing requirements, metastability protection, and operating modes, please refer to the FIFO Intel FPGA IP User Guide.

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