Parameterizable Macros for Intel FPGAs User Guide

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ID 772350
Date 4/17/2023
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Document Table of Contents
Document Table of Contents x
1. About the Parameterizable Macros for Intel FPGAs User Guide 2. List of Parameterizable Macros for Intel FPGAs 3. Inserting HDL Code from Parameterizable Macros Template 4. Dual-Port Random Access Memory (RAM) 5. FIFO 6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
4. Dual-Port Random Access Memory (RAM) x
4.1. Simple Dual-Port RAM 4.2. True Dual-Port RAM
4.1. Simple Dual-Port RAM x
4.1.1. Port Descriptions 4.1.2. Parameters 4.1.3. Instantiation Template
4.2. True Dual-Port RAM x
4.2.1. Port Description 4.2.2. Parameters 4.2.3. Instantiation Template
5. FIFO x
5.1. Asynchronous FIFO (async_fifo/ASYNC_FIFO) 5.2. Synchronous FIFO (sync_fifo/SYNC_FIFO)
5.1. Asynchronous FIFO (async_fifo/ASYNC_FIFO) x
5.1.1. Port Descriptions 5.1.2. Parameters 5.1.3. Instantiation Template
5.2. Synchronous FIFO (sync_fifo/SYNC_FIFO) x
5.2.1. Port Descriptions 5.2.2. Parameters 5.2.3. Instantiation Template
1. About the Parameterizable Macros for Intel FPGAs User Guide
2. List of Parameterizable Macros for Intel FPGAs
3. Inserting HDL Code from Parameterizable Macros Template
4. Dual-Port Random Access Memory (RAM)
5. FIFO
6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide

5. FIFO

The FIFO functions are mostly applied in data buffering applications that comply with the first-in-first-out data flow in synchronous or asynchronous clock domains. SYNC_FIFO/sync_fifo is a synchronous FIFO and uses the same clock signal to perform the read and write operations. ASYNC_FIFO/async_fifo is an asynchronous FIFO and uses the rdclk or wrclk signal to perform the read or write operation, respectively.

The parameterizable SYNC_FIFO/sync_fifo and ASYNC_FIFO/async_fifo modules can be instantiated using the instantiation templates available in Intel® Quartus® Prime Pro Edition, starting from version 23.1. The SYNC_FIFO/sync_fifo module can be instantiated using the synchronous FIFO template (sync_fifo or SYNC_FIFO), while the ASYNC_FIFO/async_fifo module can be instantiated using the asynchronous FIFO template (async_fifo or ASYNC_FIFO).

This section provides the block diagrams, port descriptions, parameter tables, and instantiation templates of the SYNC_FIFO/sync_fifo and ASYNC_FIFO/async_fifo macro modules. For more information on these FIFO modules, such as the timing requirements, metastability protection, and operating modes, please refer to the FIFO Intel FPGA IP User Guide.


Section Content
Asynchronous FIFO (async_fifo/ASYNC_FIFO)
Synchronous FIFO (sync_fifo/SYNC_FIFO)

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