| clock0 |
Input |
Yes |
The following describes which of your memory clock must be connected to the clock0 port, and port synchronization in different clocking modes:
- Single clock: Connect your single source clock to clock0 port. All registered ports are synchronized by the same source clock.
- Read/Write: Connect your read clock to clock0 port. All registered ports related to write operation, such as data_a port, address_a port, wren_a port, and byteena_a port are synchronized by the write clock.
- Input Output: Connect your input clock to clock0 port. All registered input ports are synchronized by the input clock.
- Independent clock: Connect your port A clock to clock0 port. All registered input and output ports of port A are synchronized by the port A clock.
|
| clock1 |
Input |
Optional |
The following describes which of your memory clock must be connected to the clock1 port, and port synchronization in different clocking modes:
- Single clock: Not applicable. All registered ports are synchronized by clock1 port.
- Read/Write: Connect your read clock to clock1 port. All registered ports related to read operation, such as address_b port and rden_b port are synchronized by the read clock.
- Input Output: Connect your output clock to clock1 port. All the registered output ports are synchronized by the output clock.
- Independent clock: Connect your port B clock to clock1 port. All registered input and output ports of port B are synchronized by the port B clock.
|
| clocken0 |
Input |
Optional |
Clock enable input for clock0 port. |
| clocken1 |
Input |
Optional |
Clock enable input for clock1 port. |
| aclr |
Input |
Optional |
Asynchronous clear port which asynchronously clears the registered input data output port(s) clocked by clock0. The effect of this port can be controlled through the asynchronous clear parameters:
- OUT_DATA_A_ACLR
- OUT_DATA_B_ACLR
|
| sclr |
Input |
Optional |
Synchronous clear port. Clears the registered data output ports. |
| data_a |
Input |
Yes |
Data input port at port A. |
| address_a |
Input |
Yes |
Address port at port A. |
| wren_a |
Input |
Optional (Always pull low if not connected) |
Write enable port at Port A. |
| rden_a |
Input |
Optional |
Read enable port for port A. |
| byteena_a |
Input |
Optional |
Byte enable port at Port A to mask the data_a port so that only specific bits of the data are written to the memory. |
| data_b |
Input |
Optional |
Data input port at port B. |
| address_b |
Input |
Optional |
Address port at port B. |
| wren_b |
Input |
Yes |
Write enable port at Port B. |
| rden_b |
Input |
Optional |
Read enable input for port B. |
| byteena_b |
Input |
Optional |
Byte enable port at Port B to mask the data_b port so that only specific bits of the data are written to the memory. |
| q_a |
Output |
Yes |
Data output port at port A. The width of q_a port must be equal to the width of data_a port. |
| q_b |
Output |
Yes |
Data output port at port B. The width of q_b port must be equal to the width of data_b port. |