Parameterizable Macros for Intel FPGAs User Guide

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ID 772350
Date 4/17/2023
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Document Table of Contents
Document Table of Contents x
1. About the Parameterizable Macros for Intel FPGAs User Guide 2. List of Parameterizable Macros for Intel FPGAs 3. Inserting HDL Code from Parameterizable Macros Template 4. Dual-Port Random Access Memory (RAM) 5. FIFO 6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
4. Dual-Port Random Access Memory (RAM) x
4.1. Simple Dual-Port RAM 4.2. True Dual-Port RAM
4.1. Simple Dual-Port RAM x
4.1.1. Port Descriptions 4.1.2. Parameters 4.1.3. Instantiation Template
4.2. True Dual-Port RAM x
4.2.1. Port Description 4.2.2. Parameters 4.2.3. Instantiation Template
5. FIFO x
5.1. Asynchronous FIFO (async_fifo/ASYNC_FIFO) 5.2. Synchronous FIFO (sync_fifo/SYNC_FIFO)
5.1. Asynchronous FIFO (async_fifo/ASYNC_FIFO) x
5.1.1. Port Descriptions 5.1.2. Parameters 5.1.3. Instantiation Template
5.2. Synchronous FIFO (sync_fifo/SYNC_FIFO) x
5.2.1. Port Descriptions 5.2.2. Parameters 5.2.3. Instantiation Template
1. About the Parameterizable Macros for Intel FPGAs User Guide
2. List of Parameterizable Macros for Intel FPGAs
3. Inserting HDL Code from Parameterizable Macros Template
4. Dual-Port Random Access Memory (RAM)
5. FIFO
6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide

4.2.2. Parameters

Table 4.  True Dual-Port RAM Parameterizable Macros Parameters
Name Allowed Values Description
ADDR_REG_B_CLK

CLOCK1

CLOCK0

Clock choice for address registers at Port B.
ADDR_WIDTH_A 11 Address width of Port A.
ADDR_WIDTH_B 11 Address width of Port B.
BYTE_EN_REG_B

CLOCK1

CLOCK0

Clock choice for byte enable registers at Port B.
BYTE_EN_WIDTH_A 1 Width of the byte enable bus at Port A. The width for BYTE_EN_WIDTH_A should be equal to DATA_WIDTH_A divided by BYTE_SIZE.
BYTE_EN_WIDTH_B 1

Width of the byte-enable bus at Port B. This width should be equal to DATA_WIDTH_B divided by BYTE_SIZE.

BYTE_SIZE

5

8

9

10

Specifies the size of the byte for byte-enable mode.
CLK_EN_IN_A

NORMAL

BYPASS

Specifies the clock enable being used for the input registers of Port A.
CLK_EN_IN_B

NORMAL

BYPASS

Specifies the clock enable being used for the input registers of Port B.
CLK_EN_OUT_A

NORMAL

BYPASS

Specifies the clock enable being used for the output registers of Port A.
CLK_EN_OUT_B

NORMAL

BYPASS

Specifies the clock enable being used for the output registers of Port B.
DATA_WIDTH_A 8 Data width of Port A.
DATA_WIDTH_B 8 Data width of Port B.
FORCE_TO_ZERO

TRUE

FALSE

Enables or disables the Force-to-Zero feature.

Force-to-Zero feature can help to improve the performance of glue logic when the memory depth is larger than a single memory block.

INIT_FILE_LAYOUT

PORT_A

PORT_B

UNUSED

Specifies the layout of the initialization file.
IN_DATA_REG_B_CLK

CLOCK1

CLOCK0

Clock choice for data output registers at Port B.
MAX_DEPTH 2048 Specifies the depth of the RAM slices.
MEMORY_INIT_FILE

*.mif

*.hex

UNUSED

Specifies the initialization file.
MEMORY_OPTIMIZATION

AUTO

HIGH_SPEED

LOW_POWER

Specifies how the RAM block would be optimized.
OUT_DATA_A_ACLR

NONE

CLEAR0

Asynchronous clear choice for data output registers at Port A. When OUT_DATA_REG_A_CLK is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch.
OUT_DATA_A_SCLR

NONE

SCLEAR

Synchronous clear choice for data output registers at Port A. When OUT_DATA_REG_A_CLK is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch.
OUT_DATA_B_ACLR

NONE

CLEAR0

Asynchronous clear choice for data output registers at Port B. When OUT_DATA_REG_B_CLK is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch.
OUT_DATA_B_SCLR

NONE

SCLEAR

Synchronous clear choice for data output registers at Port B. When OUT_DATA_REG_B_CLK is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch.
OUT_DATA_REG_A_CLK

UNREGISTERED

CLOCK1

CLOCK0

Clock choice for data output registers at Port A.
OUT_DATA_REG_B_CLK

UNREGISTERED

CLOCK1

CLOCK0

Clock choice for data output registers at Port B.
RAM_BLOCK_TYPE

Auto

M20K

Specifies the RAM block type.
READ_DURING_WRITE_A

NEW_DATA_NO_NBE_READ

The behavior of read-during-write mode in Port A.
READ_DURING_WRITE_B

NEW_DATA_NO_NBE_READ

The behavior of read-during-write mode in Port B.
READ_DURING_WRITE_MODE_MIXED_PORTS

DONT_CARE

The behavior of read-during-write mode in mixed-ports.
Level Two Title