Parameterizable Macros for Intel FPGAs User Guide

Download PDF
ID 772350
Date 4/17/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the Parameterizable Macros for Intel FPGAs User Guide 2. List of Parameterizable Macros for Intel FPGAs 3. Inserting HDL Code from Parameterizable Macros Template 4. Dual-Port Random Access Memory (RAM) 5. FIFO 6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
4. Dual-Port Random Access Memory (RAM) x
4.1. Simple Dual-Port RAM 4.2. True Dual-Port RAM
4.1. Simple Dual-Port RAM x
4.1.1. Port Descriptions 4.1.2. Parameters 4.1.3. Instantiation Template
4.2. True Dual-Port RAM x
4.2.1. Port Description 4.2.2. Parameters 4.2.3. Instantiation Template
5. FIFO x
5.1. Asynchronous FIFO (async_fifo/ASYNC_FIFO) 5.2. Synchronous FIFO (sync_fifo/SYNC_FIFO)
5.1. Asynchronous FIFO (async_fifo/ASYNC_FIFO) x
5.1.1. Port Descriptions 5.1.2. Parameters 5.1.3. Instantiation Template
5.2. Synchronous FIFO (sync_fifo/SYNC_FIFO) x
5.2.1. Port Descriptions 5.2.2. Parameters 5.2.3. Instantiation Template
1. About the Parameterizable Macros for Intel FPGAs User Guide
2. List of Parameterizable Macros for Intel FPGAs
3. Inserting HDL Code from Parameterizable Macros Template
4. Dual-Port Random Access Memory (RAM)
5. FIFO
6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide

6. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide

Document Version Intel® Quartus® Prime Version Changes
2023.04.17 23.1 Initial release.
Level Two Title