Intel Agilex® 7 F-Series FPGA (Two F-Tiles) Development Kit User Guide

ID 739942
Date 8/07/2023
Document Table of Contents

4.2.6. The Memory Tab

This tab allows you to read and write DDR4 DIMM1 and DDR4 DIMM2 memory on your board. Download the design through BTS Configure.

Figure 17. The RDIMM1 Tab

The following sections describe controls on this tab.


Initiates DDR4 memory transaction performance analysis.


Terminates transaction performance analysis.

Performance Indicators

These controls display current transaction performance analysis information collected since you last clicked Start:

  • Write and Read performance bars: Show the percentage of maximum theoretical data rate that the requested transactions can achieve.
  • Write (MBps) and Read (MBps): Show the number of bytes analyzed per second.
  • Data Bus: 72 bits (8 bits ECC) wide, reference clock is 166.666 MHz, and the frequency is 1333.33 MHz double data rate 2666.66 MT/s.

Test Control

  • Test Size: You can choose the size of the memory to test. The available options are 64 KB, 256 KB, 1 MB, 4 MB, 16 MB, 64 MB, 256 MB, 1 GB, 4 GB, 8 GB, and 16GB (default).
  • Offset (Hex): You can define the memory start address to test.
  • Test Mode: Infinite Read and Write (default), Single Read and Write.
  • Test Pattern: PRBS (default), User Defined Constant, Walking ‘0’, Walking ‘1'.

Error Control

This control displays data errors detected during analysis and allows you to insert errors:

  • Detected Errors: Displays the number of data errors detected in the hardware.
  • Inserted Errors: Displays the number of errors inserted into the transaction stream.
  • Bit Error Rate: Calculates the bit error rate of the transmit data stream.
  • Insert: Insert a one-word error into the transaction stream each time you click the button. Insert error is only enabled during transaction performance analysis.
  • Clear: Resets the Detected Errors counter and Inserted Errors counter to zeros.
Figure 18. The RDIMM2 TabSimilar with RDIMM1.