Intel Agilex® 7 F-Series FPGA (Two F-Tiles) Development Kit User Guide

ID 739942
Date 8/07/2023
Public
Document Table of Contents

A.3.1. Switch Description

Table 17.  SW1—4 Position DIP for PCIe* Lane Width Selection
Switch position Board Label Function Default Position
1 x16 ON for PCIe* x16 ON
2 x8 ON for PCIe* x8 OFF
3 x4 ON for PCIe* x4 OFF
4 x1 ON for PCIe* x1 OFF
Table 18.  SW2—Single DIP for Intel® FPGA Download Cable II Selection
Switch position Board Label Function Default Position
SW2 USB MAX JTAG SEL ON for on-board Intel® FPGA Download Cable II ON
OFF for external Intel® FPGA Download Cable II
Table 19.  SW3—4 position DIP for Configuration Mode Selection and JTAG ControlBy default, MSEL[2:0] is set to '001' for AS x4 with CvP support. MSEL0 is tied to logic high.
Switch position Board Label Function Default Position
1 MSEL1 Configuration MSEL1 ON
2 MSEL2 Configuration MSEL2 ON
3 BMC JTAG SEL ON Selects On-board Blaster ON
4 HPS JTAG BYPASS OFF Bypass HPS JTAG OFF

The board only supports the following configuration modes.

Table 20.  Supported Configuration Modes MSEL0 is tied to logic high.
Configuration Mode MSEL2 MSEL1 MSEL0
JTAG 1 1 1
Avalon® -ST x16 1 0 1
AS x4 Fast (CVP support) 0 0 1
AS x4 Normal 0 1 1
Table 21.  SW4
Switch position Board Label Function Default Position
1 SSEN ON enables PCIe* Spread Spectrum OFF
2 CXL REFCLK Select ON for local PCIe* REFCLK on Bank12C OFF
3 PCIe* REFCLK Select ON for local PCIe* REFCLK on Bank13A OFF
4 PCIe* Clock Power-down On powers down PCIe* clock sources OFF
Table 22.  SW5—Slide Switch to Power On the Board
Switch position Board Label Function Default Position
SW5 Power On ON to power on the board OFF
Table 23.  SW6—Single DIP for Intel® MAX® 10 JTAG Enable
Switch position Board Label Function Default Position
SW6 Intel® MAX® 10 JTAG Enable ON to share Intel® MAX® 10 JTAG Pins OFF
Table 24.  S[1–4, 6]—Various Push-Button RESET Switches
Switch Function
S1 Used to send RESET to CPU
S2 Used to send RESET to HPS
S3 Used to send PERSTN to PCIe*
S4 Used to send 2nd PERSTN to PCIe*
S6 Used to send PERSTN to CXL PCIe*