Intel Agilex® 7 F-Series FPGA (Two F-Tiles) Development Kit User Guide

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ID 739942
Date 8/07/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Power Up the Development Kit 4. Board Test System 5. Development Kits Hardware and Configuration 6. Custom Projects for the Development Kit 7. Revision History A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Intel® Quartus® Prime Software and Driver Installation 2.2. Design Examples
3. Power Up the Development Kit x
3.1. Default Settings 3.2. Applying Power to the Development Board
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass- or Fail-based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Download OpenJDK 4.1.2. Download OpenJFX 4.1.3. Install OpenJDK and OpenJFX 4.1.4. Install the Intel® Quartus® Prime Software 4.1.5. Run BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFP NRZ Tab 4.2.5.2. The QSFP PAM4 Tab 4.2.5.3. The QSFPDD NRZ Tab 4.2.5.4. The QSFPDD PAM4 Tab
5. Development Kits Hardware and Configuration x
5.1. JTAG Configuration Mode 5.2. Active Serial (AS) x4 Configuration Mode 5.3. Avalon® -ST x16 Configuration Mode
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Intel® Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. FPGA Configuration A.3. Default Switch and Jumper Settings A.4. Input and Output Components A.5. Components and Interfaces A.6. I2C A.7. Intel® MAX® 10 SPI Bus A.8. Clock Circuits A.9. HPS Daughter Card A.10. System Power A.11. Power Guidelines A.12. Power Distribution System A.13. Power Measurement A.14. Thermal Limitations and Protection
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components A.1.3. Intel® MAX® 10 CPLD System Controller
A.2. FPGA Configuration x
A.2.1. Programming the FPGA over On-Board Intel® FPGA Download Cable II A.2.2. Programming the FPGA over an External Intel® FPGA Download Cable II
A.3. Default Switch and Jumper Settings x
A.3.1. Switch Description A.3.2. Jumper Description
A.4. Input and Output Components x
A.4.1. Push Buttons A.4.2. Switches A.4.3. LEDs
A.5. Components and Interfaces x
A.5.1. PCI Express* ( PCIe* ) Interface A.5.2. QSFP-DD Interface A.5.3. QSFP Interface A.5.4. CXL Interface A.5.5. DDR4 DIMM1 Interface A.5.6. DDR4 DIMM2 Interface A.5.7. DDR4 Component Interface A.5.8. HPS I/O48 Interface
A.11. Power Guidelines x
A.11.1. In a Standard PCIe* -Compliant System A.11.2. As a Standalone Evaluation Board Powered by Included Power Supply
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Power Up the Development Kit
4. Board Test System
5. Development Kits Hardware and Configuration
6. Custom Projects for the Development Kit
7. Revision History
A. Development Kit Components
B. Additional Information

A.5.4. CXL Interface

The Intel Agilex® 7 FPGA (two F-tiles) development board provides a CXL connector interface for cabling to an Intel® -designed M.2 SSD daughter card supporting M-Keying. This interface connects to four 28 Gbps F-tile lanes of the Intel Agilex® 7 FPGA. When connecting the development board to this SSD daughter card, the development board connects four transceiver channels from the F-tile bank 12C to M2 channels 8-11 (J5) of the M.2 daughter card.

Table 32.  CXL Pin Assignments
Schematic Signal Name FPGA Pin Number I/O Standard Description
CXL_TX_P0 BW49 True Differential Signaling CXL Transmit Channel 0 Positive
CXL_TX_N0 BY48 True Differential Signaling CXL Transmit Channel 0 Negative
CXL_TX_P1 BV52 True Differential Signaling CXL Transmit Channel 1 Positive
CXL_TX_N1 BU51 True Differential Signaling CXL Transmit Channel 1 Negative
CXL_TX_P2 BR49 True Differential Signaling CXL Transmit Channel 2 Positive
CXL_TX_N2 BT48 True Differential Signaling CXL Transmit Channel 2 Negative
CXL_TX_P3 BP52 True Differential Signaling CXL Transmit Channel 3 Positive
CXL_TX_N3 BN51 True Differential Signaling CXL Transmit Channel 3 Negative
CXL_RX_P0 CC55 True Differential Signaling CXL Receive Channel 0
Positive
CXL_RX_N0 CD54 True Differential Signaling CXL Receive Channel 0 Negative
CXL_RX_P1 CB52 True Differential Signaling CXL Receive Channel 1
Positive
CXL_RX_N1 CA51 True Differential Signaling CXL Receive Channel 1 Negative
CXL_RX_P2 BW55 True Differential Signaling CXL Receive Channel 2
Positive
CXL_RX_N2 BY54 True Differential Signaling CXL Receive Channel 2 Negative
CXL_RX_P3 BR55 True Differential Signaling CXL Receive Channel 3
Positive
CXL_RX_N3 BT54 True Differential Signaling CXL Receive Channel 3 Negative
REFCLK_CXL_EP_P BC49 100 MHz LVPECL CXL Reference Clock
Positive, Local board clock
REFCLK_CXL_EP_N BE49 100 MHz LVPECL CXL Reference Clock
Negative, Local board clock
REFCLK_CXL_CONN_P BG49 100 MHz LVPECL CXL Reference Clock
Positive, Remote board clock
REFCLK_CLK_CONN_N BF48 100 MHz LVPECL CXL Reference Clock
Negative, Remote board clock
CXL_PERSTN D43 1.2 V HS LVCMOS CXL Reset
CXL_PRSNTx4_N F50 1.2 V HS LVCMOS CXL Present
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