Intel Agilex® 7 F-Series FPGA (Two F-Tiles) Development Kit User Guide

ID 739942
Date 8/07/2023
Public
Document Table of Contents

5.1. JTAG Configuration Mode

When MSEL[2:1] are both set to logic high by DIP switch SW3[2:1] = [OFF:OFF], the configuration mode defaults to JTAG.