Intel Agilex® 7 F-Series FPGA (Two F-Tiles) Development Kit User Guide

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ID 739942
Date 8/07/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Power Up the Development Kit 4. Board Test System 5. Development Kits Hardware and Configuration 6. Custom Projects for the Development Kit 7. Revision History A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Intel® Quartus® Prime Software and Driver Installation 2.2. Design Examples
3. Power Up the Development Kit x
3.1. Default Settings 3.2. Applying Power to the Development Board
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass- or Fail-based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Download OpenJDK 4.1.2. Download OpenJFX 4.1.3. Install OpenJDK and OpenJFX 4.1.4. Install the Intel® Quartus® Prime Software 4.1.5. Run BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFP NRZ Tab 4.2.5.2. The QSFP PAM4 Tab 4.2.5.3. The QSFPDD NRZ Tab 4.2.5.4. The QSFPDD PAM4 Tab
5. Development Kits Hardware and Configuration x
5.1. JTAG Configuration Mode 5.2. Active Serial (AS) x4 Configuration Mode 5.3. Avalon® -ST x16 Configuration Mode
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Intel® Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Board Overview and Components A.2. FPGA Configuration A.3. Default Switch and Jumper Settings A.4. Input and Output Components A.5. Components and Interfaces A.6. I2C A.7. Intel® MAX® 10 SPI Bus A.8. Clock Circuits A.9. HPS Daughter Card A.10. System Power A.11. Power Guidelines A.12. Power Distribution System A.13. Power Measurement A.14. Thermal Limitations and Protection
A.1. Board Overview and Components x
A.1.1. Board Overview A.1.2. Board Components A.1.3. Intel® MAX® 10 CPLD System Controller
A.2. FPGA Configuration x
A.2.1. Programming the FPGA over On-Board Intel® FPGA Download Cable II A.2.2. Programming the FPGA over an External Intel® FPGA Download Cable II
A.3. Default Switch and Jumper Settings x
A.3.1. Switch Description A.3.2. Jumper Description
A.4. Input and Output Components x
A.4.1. Push Buttons A.4.2. Switches A.4.3. LEDs
A.5. Components and Interfaces x
A.5.1. PCI Express* ( PCIe* ) Interface A.5.2. QSFP-DD Interface A.5.3. QSFP Interface A.5.4. CXL Interface A.5.5. DDR4 DIMM1 Interface A.5.6. DDR4 DIMM2 Interface A.5.7. DDR4 Component Interface A.5.8. HPS I/O48 Interface
A.11. Power Guidelines x
A.11.1. In a Standard PCIe* -Compliant System A.11.2. As a Standalone Evaluation Board Powered by Included Power Supply
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Power Up the Development Kit
4. Board Test System
5. Development Kits Hardware and Configuration
6. Custom Projects for the Development Kit
7. Revision History
A. Development Kit Components
B. Additional Information

A.8. Clock Circuits

Figure 26.  Intel Agilex® 7 F-Series FPGA Development Kit Clocks and Default Frequencies
Table 40.  On-Board Oscillators Sources for the FPGA
Source Schematic Signal Name Frequency I/O Standard Intel Agilex® 7 Pin Number (P/N) Application
U23 TOD_MASTER_CLK_125M_P/N 125 Mhz Differential G43/F44 IEEE 1588 TOD master clock
CLK_FPGA_100M_P/N 100 Mhz LVDS CK18/CL19 General-purpose FPGA clock
PTP_SAMPLE_CLK_250M_P/N 250 Mhz Differential E45/D46 IEEE 1588 PTP clock
DDR4_DIMM1_REFCLK_P/N 166.625 Mhz LVDS CV28/CW29 DDR4 DIMM1 clock
DDR4_DIMM2_REFCLK_P/N 166.625 Mhz LVDS DD36/DC37 DDR4 DIMM2 clock
DDR4_COMP_REFCLK_P/N 166.625 Mhz LVDS U5/T6 DDR4 component clock
QSFP_REFCLK_P/N 156.25 Mhz Differential AW49/AV48 QSFP clock
QSFPDD_REFCLK_P/N 156.25 Mhz Differential AD48/AC49 QSFPDD clock
CIPRI_HIGH_REFCLK_P/N 184.32 Mhz Differential AJ48/AH49 CIPRI high clock
CIPRI_LOW_REFCLK_P/N 153.6 Mhz Differential AR49/AU49 CIPRI low clock
U27 REFCLK_CXL_CONN_P/N 100 Mhz HCSL BG49/BF48 PCIe* REFCLK bank 12C channel 1
REFCLK_CXL_EP_P/N 100 Mhz HCSL BC49/BE49 PCIe* REFCLK bank 12C channel 0
U26 REFCLK_PCIE_13A_CH2_P/N 100 Mhz HCSL BR7/BU7 PCIe* REFCLK bank 13A channel 2
REFCLK_PCIE_13A_CH5_P/N 100 Mhz HCSL CD8/CC7 PCIe* REFCLK bank 13A channel 5
U10 FPGA_OSC_CLK1 125 Mhz 1.8 V LVCMOS CB42 Configuration clock
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