Intel Agilex® 7 F-Series FPGA (Two F-Tiles) Development Kit User Guide

ID 739942
Date 8/07/2023
Document Table of Contents

A.8. Clock Circuits

Figure 26.  Intel Agilex® 7 F-Series FPGA Development Kit Clocks and Default Frequencies
Table 40.  On-Board Oscillators Sources for the FPGA
Source Schematic Signal Name Frequency I/O Standard Intel Agilex® 7 Pin Number (P/N) Application
U23 TOD_MASTER_CLK_125M_P/N 125 Mhz Differential G43/F44 IEEE 1588 TOD master clock
CLK_FPGA_100M_P/N 100 Mhz LVDS CK18/CL19 General-purpose FPGA clock
PTP_SAMPLE_CLK_250M_P/N 250 Mhz Differential E45/D46 IEEE 1588 PTP clock
DDR4_DIMM1_REFCLK_P/N 166.625 Mhz LVDS CV28/CW29 DDR4 DIMM1 clock
DDR4_DIMM2_REFCLK_P/N 166.625 Mhz LVDS DD36/DC37 DDR4 DIMM2 clock
DDR4_COMP_REFCLK_P/N 166.625 Mhz LVDS U5/T6 DDR4 component clock
QSFP_REFCLK_P/N 156.25 Mhz Differential AW49/AV48 QSFP clock
QSFPDD_REFCLK_P/N 156.25 Mhz Differential AD48/AC49 QSFPDD clock
CIPRI_HIGH_REFCLK_P/N 184.32 Mhz Differential AJ48/AH49 CIPRI high clock
CIPRI_LOW_REFCLK_P/N 153.6 Mhz Differential AR49/AU49 CIPRI low clock
U27 REFCLK_CXL_CONN_P/N 100 Mhz HCSL BG49/BF48 PCIe* REFCLK bank 12C channel 1
REFCLK_CXL_EP_P/N 100 Mhz HCSL BC49/BE49 PCIe* REFCLK bank 12C channel 0
U26 REFCLK_PCIE_13A_CH2_P/N 100 Mhz HCSL BR7/BU7 PCIe* REFCLK bank 13A channel 2
REFCLK_PCIE_13A_CH5_P/N 100 Mhz HCSL CD8/CC7 PCIe* REFCLK bank 13A channel 5
U10 FPGA_OSC_CLK1 125 Mhz 1.8 V LVCMOS CB42 Configuration clock