Visible to Intel only — GUID: aeg1636516591717
Ixiasoft
2.1. Intel Agilex® 7 F-Tile DisplayPort SST Parallel Loopback Design Features
2.2. Intel Agilex® 7 F-Tile DisplayPort SST TX-only Design Features
2.3. Intel Agilex® 7 F-Tile DisplayPort SST RX-only Design Features
2.4. Design Components
2.5. Clocking Scheme
2.6. Interface Signals and Parameters
2.7. Simulation Testbench
Visible to Intel only — GUID: aeg1636516591717
Ixiasoft
2. DisplayPort Intel® FPGA IP Design Examples
The DisplayPort Intel FPGA IP design examples demonstrate parallel loopback from DisplayPort RX instance to DisplayPort TX instance without a Pixel Clock Recovery (PCR) module.
The DisplayPort Intel® FPGA IP TX-only design example demonstrates the DisplayPort source transmitting a fixed video resolution.
The DisplayPort Intel® FPGA IP RX-only design example demonstrates the DisplayPort sink receiving video frame from external sources.
Design Example | Designation | Data Rate | Channel Mode | Loopback Type |
---|---|---|---|---|
DisplayPort SST parallel loopback without PCR | DisplayPort SST | RBR, HBR, HBR2, HBR3, UHBR10 | Simplex | Parallel without PCR |
DisplayPort SST parallel loopback with AXIS Video Interface | DisplayPort SST | RBR, HBR, HBR2, HBR3, UHBR10 | Simplex | Parallel with AXIS Video Interface |
DisplayPort SST TX-only | DisplayPort SST | RBR, HBR, HBR2, HBR3, UHBR10 | Simplex | — |
DisplayPort SST RX-only | DisplayPort SST | RBR, HBR, HBR2, HBR3, UHBR10 | Simplex | — |