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2.1. Intel Agilex® 7 F-Tile DisplayPort SST Parallel Loopback Design Features
2.2. Intel Agilex® 7 F-Tile DisplayPort SST TX-only Design Features
2.3. Intel Agilex® 7 F-Tile DisplayPort SST RX-only Design Features
2.4. Design Components
2.5. Clocking Scheme
2.6. Interface Signals and Parameters
2.7. Simulation Testbench
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3.4.3.2.2. Key Programmer
Refer to the DisplayPort Intel Arria 10 FPGA IP Design Example User Guide or DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide for Key Programmer usage.