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2.1. Intel Agilex® 7 F-Tile DisplayPort SST Parallel Loopback Design Features
2.2. Intel Agilex® 7 F-Tile DisplayPort SST TX-only Design Features
2.3. Intel Agilex® 7 F-Tile DisplayPort SST RX-only Design Features
2.4. Design Components
2.5. Clocking Scheme
2.6. Interface Signals and Parameters
2.7. Simulation Testbench
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2.2. Intel Agilex® 7 F-Tile DisplayPort SST TX-only Design Features
The TX-only design example demonstrates the transmission of a single video stream from DisplayPort Sink to DisplayPort Source.
Figure 8. Intel Agilex® 7 DisplayPort SST TX-only
- To generate this TX-only variant, turn on the DisplayPort source TX SUPPORT DP parameter and turn off the DisplayPort sink RX SUPPORT DP parameter.
- This variant uses the standard VSYNC/HSYNC/DE video interface, while the DisplayPort source’s TX SUPPORT IM ENABLE parameter is turned off.
- For video source, this variant integrates Test Pattern Generator II and Clocked Video Output II to display 1080p60 color bar image.
- The IOPLL drives the video clock at a 300 MHz to CVO II and 37.125 MHz (4 pixel per clock) to TPG II.
- Before programming SOF file to the development kit, set OUT6 frequency of Si5391A to 150 MHz in the Clock Control GUI.