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Ixiasoft
2.1. Intel Agilex® 7 F-Tile DisplayPort SST Parallel Loopback Design Features
2.2. Intel Agilex® 7 F-Tile DisplayPort SST TX-only Design Features
2.3. Intel Agilex® 7 F-Tile DisplayPort SST RX-only Design Features
2.4. Design Components
2.5. Clocking Scheme
2.6. Interface Signals and Parameters
2.7. Simulation Testbench
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1.1. Directory Structure
Figure 2. Directory Structure
Folders | Files |
---|---|
rtl/core | dp_core.ip |
dp_rx.ip | |
dp_tx.ip | |
rtl/rx_phy | dp_gxb_rx/ ((DP PMA UX building block) |
dp_rx_data_fifo.ip | |
rx_top_phy.sv | |
rtl/tx_phy | dp_gxb_rx/ ((DP PMA UX building block) |
dp_tx_data_fifo.ip | |
dp_tx_data_fifo.ip |