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2.1. Intel Agilex® 7 F-Tile DisplayPort SST Parallel Loopback Design Features
2.2. Intel Agilex® 7 F-Tile DisplayPort SST TX-only Design Features
2.3. Intel Agilex® 7 F-Tile DisplayPort SST RX-only Design Features
2.4. Design Components
2.5. Clocking Scheme
2.6. Interface Signals and Parameters
2.7. Simulation Testbench
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3.4. Design Walkthrough
Setting up and running the HDCP over DisplayPort design example consists of five stages.
- Set up the hardware.
- Generate the design.
- Edit the HDCP key memory files to include your HDCP production keys.
- Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0)
- Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
- Compile the design.
- View the results.