F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

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ID 709308
Date 11/03/2023
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. DisplayPort Intel® FPGA IP Design Examples 3. HDCP Over DisplayPort Design Example 4. Document Revision History for F-Tile DisplayPort Intel® FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. DisplayPort Intel® FPGA IP Design Examples x
2.1. Intel Agilex® 7 F-Tile DisplayPort SST Parallel Loopback Design Features 2.2. Intel Agilex® 7 F-Tile DisplayPort SST TX-only Design Features 2.3. Intel Agilex® 7 F-Tile DisplayPort SST RX-only Design Features 2.4. Design Components 2.5. Clocking Scheme 2.6. Interface Signals and Parameters 2.7. Simulation Testbench
3. HDCP Over DisplayPort Design Example x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios® II Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Set Up the Hardware 3.4.2. Generate the Design 3.4.3. Include HDCP Production Keys 3.4.4. Compile the Design 3.4.5. View the Results
3.4.3. Include HDCP Production Keys x
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.4.5. View the Results x
3.4.5.1. LED Functions
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Intel® FPGA IP Design Examples
3. HDCP Over DisplayPort Design Example
4. Document Revision History for F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

3.6.2. Modifying HDCP Software Parameters

To facilitate the HDCP debugging process, you can modify the parameters in hdcp.c. The following table summarizes the list of configurable parameters and their functions:

Parameter Function
SUPPORT_HDCP1X Enable HDCP 1.3 on TX side
SUPPORT_HDCP2X Enable HDCP 2.3 on TX side
DEBUG_MODE_HDCP Enable debug messages for TX HDCP
REPEATER_MODE Enable repeater mode for HDCP design example

To modify the parameters, change the values to the desired values in hdcp.c. Before starting the compilation, make the following changes in the build_sw_hdcp.sh:

  1. Locate the following line and comment it out to prevent the modified software file being replaced by the original files from the Intel® Quartus® Prime software installation path:
  2. Run “./build_sw_hdcp.sh” to compile the updated software.
  3. The generated .elf file can be included into the design through two methods:
    1. Run “nios2-download -g <elf file name>”. Reset the system after the downloading process is completed to ensure proper functionality.
    2. Run “quartus_cdb –-update_mif” to update the memory initialization files. Run assembler to generate new .sof file which includes the updated software.
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