F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

ID 709308
Date 11/03/2023
Public
Document Table of Contents
Give Feedback

1.5. Compiling and Testing the Design

Figure 5. Compiling and Simulating the Design
To compile and run a demonstration test on the hardware example design, follow these steps:
  1. Ensure hardware example design generation is complete.
  2. Launch the Intel® Quartus® Prime Pro Edition software and open <project>/quartus/agi_dp_demo.qpf.
  3. Click Processing > Start Compilation.
  4. After successful compilation, the Intel® Quartus® Prime Pro Edition software generates a .sof file in your specified directory.
  5. Connect the DisplayPort RX connector on the Bitec daughter card to an external DisplayPort source, such as the graphics card on a PC.
  6. Connect the DisplayPort TX connector on the Bitec daughter card to a DisplayPort sink device, such as a video analyzer or a PC monitor.
  7. Ensure all switches on the development board are in default position.
  8. Configure Clock Controller GUI Si5391A OUT6 to 150 MHz.
  9. Configure the selected Intel Agilex® 7 F-Tile device on the development board using the generated .sof file (Tools ➤ Programmer ).
  10. The DisplayPort sink device displays the video generated from the video source.