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2.1. Intel Agilex® 7 F-Tile DisplayPort SST Parallel Loopback Design Features
2.2. Intel Agilex® 7 F-Tile DisplayPort SST TX-only Design Features
2.3. Intel Agilex® 7 F-Tile DisplayPort SST RX-only Design Features
2.4. Design Components
2.5. Clocking Scheme
2.6. Interface Signals and Parameters
2.7. Simulation Testbench
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2.3. Intel Agilex® 7 F-Tile DisplayPort SST RX-only Design Features
This RX-only design example demonstrates the transmission of a single video stream from DisplayPort sink.
Figure 9. Intel Agilex® 7 DisplayPort SST RX-only
- To generate this RX-only variant, turn on the DisplayPort sink RX SUPPORT DP and the DisplayPort source TX SUPPORT DP parameters.
- This variant uses the standard VSYNC/HSYNC/DE video interface, while the DisplayPort source TX SUPPORT IM ENABLE parameter is turned off.
- The IOPLL drives video clock at a fixed frequency (in this case, 300 MHz by default).
- If you configure the DisplayPort sink MAX LINK RATE parameter to HBR3 or MAX LINK RATE parameter to HBR2 and PIXELS PER CLOCK to DUAL, the video clock runs at 300 MHz to support 4Kp60 pixel rate (594/2 = 297 MHz). Otherwise, the video clock runs at 160 MHz.
- The DisplayPort sink receives video from an external video source such as a GPU and decodes it for the parallel video interface.