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2.1. Intel Agilex® 7 F-Tile DisplayPort SST Parallel Loopback Design Features
2.2. Intel Agilex® 7 F-Tile DisplayPort SST TX-only Design Features
2.3. Intel Agilex® 7 F-Tile DisplayPort SST RX-only Design Features
2.4. Design Components
2.5. Clocking Scheme
2.6. Interface Signals and Parameters
2.7. Simulation Testbench
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3.4.5. View the Results
At the end of the demonstration, you will be able to view the results on the HDCP-enabled DisplayPort external sink.
To view the results of the demonstration, follow these steps:
- Power up the Intel FPGA board.
- Change the directory to <project directory>/quartus/ directory.
- Type the following command on the Nios II Command Shell to download the Software Object File (.sof) to the FPGA.
nios2-configure-sof <Intel Quartus Prime project name>.sof
- Power up the HDCP-enabled DisplayPort external source and sink (if you have not done so). The DisplayPort external sink displays the output of your DisplayPort external source.