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2.1. Intel Agilex® 7 F-Tile DisplayPort SST Parallel Loopback Design Features
2.2. Intel Agilex® 7 F-Tile DisplayPort SST TX-only Design Features
2.3. Intel Agilex® 7 F-Tile DisplayPort SST RX-only Design Features
2.4. Design Components
2.5. Clocking Scheme
2.6. Interface Signals and Parameters
2.7. Simulation Testbench
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4. Document Revision History for F-Tile DisplayPort Intel® FPGA IP Design Example User Guide
Document Version | Intel® Quartus® Prime Version | IP Version | Changes |
---|---|---|---|
2023.11.03 | 23.3 | 20.0.1 |
|
2023.04.18 | 23.1 | 20.0.1 |
|
2022.10.21 | 22.3 | 20.0.1 | Enabled DisplayPort 2.0 UHBR10 data rate in design examples. |
2022.09.02 | 22.2 | 20.0.1 |
|
2021.12.13 | 21.4 | 20.0.0 | Initial release. |