F-Tile DisplayPort IP Design Example User Guide

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ID 709308
Date 12/01/2025
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort IP Design Example Quick Start Guide 2. DisplayPort IP Design Examples 3. Display Stream Compression (DSC) Support 4. HDCP Over DisplayPort Design Example 5. Document Revision History for F-Tile DisplayPort IP Design Example User Guide
1. DisplayPort IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. DisplayPort IP Design Examples x
2.1. Agilex™ 7 F-Tile DisplayPort SST Parallel Loopback Design Features 2.2. Agilex™ 7 F-Tile DisplayPort SST TX-only Design Features 2.3. Agilex™ 7 F-Tile DisplayPort SST RX-only Design Features 2.4. Design Components 2.5. Clocking Scheme 2.6. Interface Signals and Parameters 2.7. Simulation Testbench
4. HDCP Over DisplayPort Design Example x
4.1. High-bandwidth Digital Content Protection (HDCP) 4.2. HDCP Over DisplayPort Design Example Architecture 4.3. Nios® V Processor Software Flow 4.4. Design Walkthrough 4.5. Protection of Encryption Key Embedded in FPGA Design 4.6. Debug Guidelines
4.4. Design Walkthrough x
4.4.1. Setting Up the Hardware 4.4.2. Generating the Design 4.4.3. Including HDCP Production Keys 4.4.4. Compiling the Design 4.4.5. Viewing the Results
4.4.3. Including HDCP Production Keys x
4.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) 4.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1)
4.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) x
4.4.3.1.1. HDCP Key Mapping from DCP Key Files 4.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 4.4.3.1.3. hdcp2x_rx_kmem.v file 4.4.3.1.4. hdcp2x_tx_kmem.v file
4.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1) x
4.4.3.2.1. Altera® KEYENC 4.4.3.2.2. Key Programmer
4.5. Protection of Encryption Key Embedded in FPGA Design x
4.5.1. Security Considerations
4.6. Debug Guidelines x
4.6.1. HDCP Status Signals 4.6.2. Modifying HDCP Software Parameters 4.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort IP Design Example Quick Start Guide
2. DisplayPort IP Design Examples
3. Display Stream Compression (DSC) Support
4. HDCP Over DisplayPort Design Example
5. Document Revision History for F-Tile DisplayPort IP Design Example User Guide

2.2. Agilex™ 7 F-Tile DisplayPort SST TX-only Design Features

The TX-only design example demonstrates the transmission of a single video stream from the Altera® DisplayPort Source IP to an external DisplayPort Sink.
Figure 8.  Agilex™ 7 DisplayPort SST TX-only
  • To generate this TX-only variant, turn on the DisplayPort source TX SUPPORT DP parameter and turn off the DisplayPort sink RX SUPPORT DP parameter.
  • This variant uses the standard VSYNC/HSYNC/DE video interface, while the DisplayPort source’s TX SUPPORT IM ENABLE parameter is turned off.
  • For video source, this variant integrates Test Pattern Generator II and Clocked Video Output II to display 1080p60 color bar image.
  • The IOPLL drives the video clock at a 300 MHz to CVO II and 37.125 MHz (4 pixel per clock) to TPG II.

    In earlier versions of this design, you had to set OUT6 frequency of Si5391A to 150 MHz in the Clock Control GUI before programming the SOF file to the development kit. As of Quartus® Prime Pro Edition version 24.3.1 and later versions, this clock is configured automatically by the Nios® V processor.

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