F-Tile DisplayPort IP Design Example User Guide

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ID 709308
Date 12/01/2025
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort IP Design Example Quick Start Guide 2. DisplayPort IP Design Examples 3. Display Stream Compression (DSC) Support 4. HDCP Over DisplayPort Design Example 5. Document Revision History for F-Tile DisplayPort IP Design Example User Guide
1. DisplayPort IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. DisplayPort IP Design Examples x
2.1. Agilex™ 7 F-Tile DisplayPort SST Parallel Loopback Design Features 2.2. Agilex™ 7 F-Tile DisplayPort SST TX-only Design Features 2.3. Agilex™ 7 F-Tile DisplayPort SST RX-only Design Features 2.4. Design Components 2.5. Clocking Scheme 2.6. Interface Signals and Parameters 2.7. Simulation Testbench
4. HDCP Over DisplayPort Design Example x
4.1. High-bandwidth Digital Content Protection (HDCP) 4.2. HDCP Over DisplayPort Design Example Architecture 4.3. Nios® V Processor Software Flow 4.4. Design Walkthrough 4.5. Protection of Encryption Key Embedded in FPGA Design 4.6. Debug Guidelines
4.4. Design Walkthrough x
4.4.1. Setting Up the Hardware 4.4.2. Generating the Design 4.4.3. Including HDCP Production Keys 4.4.4. Compiling the Design 4.4.5. Viewing the Results
4.4.3. Including HDCP Production Keys x
4.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) 4.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1)
4.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) x
4.4.3.1.1. HDCP Key Mapping from DCP Key Files 4.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 4.4.3.1.3. hdcp2x_rx_kmem.v file 4.4.3.1.4. hdcp2x_tx_kmem.v file
4.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1) x
4.4.3.2.1. Altera® KEYENC 4.4.3.2.2. Key Programmer
4.5. Protection of Encryption Key Embedded in FPGA Design x
4.5.1. Security Considerations
4.6. Debug Guidelines x
4.6.1. HDCP Status Signals 4.6.2. Modifying HDCP Software Parameters 4.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort IP Design Example Quick Start Guide
2. DisplayPort IP Design Examples
3. Display Stream Compression (DSC) Support
4. HDCP Over DisplayPort Design Example
5. Document Revision History for F-Tile DisplayPort IP Design Example User Guide

1.4. Simulating the Design

The DisplayPort IP design example testbench simulates a serial loopback design from a TX instance to an RX instance. An internal video pattern generator module drives the DisplayPort TX instance and the RX instance video output connects to CRC checkers in the testbench. The testbench will stimulate rates up to and including the maximum rate selected in the IP GUI.
Figure 4. Design Simulation Flow
  1. Navigate to the simulation folder of your choice.
  2. Run the simulation script for the supported simulator. The script compiles and runs the testbench in the simulator.
  3. Analyze the results.
Table 2.  Steps to Run Simulation
Simulator Working Directory Instructions
Riviera-PRO* /simulation/aldec In the command line, type
vsim -c -do aldec.do
ModelSim* /simulation/mentor In the command line, type
vsim -c -do mentor.do
Xcelium /simulation/xcelium
In the command line, type 
source xcelium.sh
VCS /simulation/synopsys/vcs
In the command line, type 
source vcs_sim.sh
VCS MX /simulation/synopsys/vcsmx
In the command line, type 
source vcsmx_sim.sh

A successful simulation ends with the following message:

# SINK CRC_R = ac9c, CRC_G = ac9c, CRC_B = ac9c,
# SOURCE CRC_R = ac9c, CRC_G = ac9c, CRC_B = ac9c,
# Pass: Test Completed
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