4G Turbo-V Intel® FPGA IP User Guide

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ID 683882
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 4G Turbo-V Intel® FPGA IP 2. Getting Started with 4G Turbo-V IP 3. Designing with the 4G Turbo-V Intel® FPGA IP 4. 4G Turbo-V Intel® FPGA IP Functional Description 5. 4G Turbo-V Intel FPGA IP User Guide Document Archive 6. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide
1. About the 4G Turbo-V Intel® FPGA IP x
1.1. 4G Turbo-V Intel® FPGA IP Features 1.2. 4G Turbo-V Intel® FPGA IP Device Family Support 1.3. 4G Turbo-V IP Release Information 1.4. 4G Turbo-V Performance and Resource Utilization
2. Getting Started with 4G Turbo-V IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 4G Turbo-V IP Timeout Behavior
3. Designing with the 4G Turbo-V Intel® FPGA IP x
3.1. Generating a 4G Turbo-V IP 3.2. Simulating the IP with the RTL Simulator 3.3. Simulating a 4G Turbo-V IP with MATLAB 3.4. Simulating a 4G Turbo-V IP with C-Models
4. 4G Turbo-V Intel® FPGA IP Functional Description x
4.1. 4G Turbo-V Downlink Accelerator 4.2. 4G Turbo-V Uplink Accelerator 4.3. 4G Turbo-V Signals and Interfaces
4.1. 4G Turbo-V Downlink Accelerator x
4.1.1. Turbo Encoder 4.1.2. Rate Matcher 4.1.3. Input and Output Data Formats 4.1.4. Latency Calculations 4.1.5. Throughput Calculations
4.2. 4G Turbo-V Uplink Accelerator x
4.2.1. Turbo Decoder 4.2.2. Input and Output Data Formats 4.2.3. Latency Calculations 4.2.4. Throughput Calculations
4.3. 4G Turbo-V Signals and Interfaces x
4.3.1. Avalon Streaming Interfaces in DSP Intel FPGA IP
1. About the 4G Turbo-V Intel® FPGA IP
2. Getting Started with 4G Turbo-V IP
3. Designing with the 4G Turbo-V Intel® FPGA IP
4. 4G Turbo-V Intel® FPGA IP Functional Description
5. 4G Turbo-V Intel FPGA IP User Guide Document Archive
6. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide

3.3. Simulating a 4G Turbo-V IP with MATLAB

Before simulating, generate a design example from the IP parameter editor. No hardware example gets generated when you click Generate Example Design. If you upgrade the IP to a newer version, regenerate the example design. This task is for simulating an uplink accelerator. To simulate an downlink accelerator replace ul with dl in each directory or file name.
Run the MATLAB script from the <Example Design Folder>\matlab\ directory in MATLAB.
>> main_turbov_ul
The MATLAB model reads and generates the same .txt files as the C model.
You can use the MATLAB generate_test_data.m to generate different test data. Newly generated .txt files replace the existing ones in the <Example Design Folder>\test_data directory.
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