Visible to Intel only — GUID: sym1587041716609
Ixiasoft
Visible to Intel only — GUID: sym1587041716609
Ixiasoft
4.1. 4G Turbo-V Downlink Accelerator
The 4G downlink accelerator implements a code block CRC attachment with 8-bit parallel CRC computation algorithm. The input to the CRC attachment block is 8-bit wide. In the normal mode, the number of inputs to the CRC block is K-24, where K is the block size based on the size index. The additional CRC sequence of 24 bits is attached to the incoming code block of data in the CRC attachment block and then passes to the Turbo encoder. In the CRC bypass mode, the number of inputs is K size of 8-bit wide passed to the Turbo encoder block.
Section Content
Turbo Encoder
Rate Matcher
Input and Output Data Formats
Latency Calculations
Throughput Calculations