4G Turbo-V Intel® FPGA IP User Guide

Download PDF
ID 683882
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 4G Turbo-V Intel® FPGA IP 2. Getting Started with 4G Turbo-V IP 3. Designing with the 4G Turbo-V Intel® FPGA IP 4. 4G Turbo-V Intel® FPGA IP Functional Description 5. 4G Turbo-V Intel FPGA IP User Guide Document Archive 6. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide
1. About the 4G Turbo-V Intel® FPGA IP x
1.1. 4G Turbo-V Intel® FPGA IP Features 1.2. 4G Turbo-V Intel® FPGA IP Device Family Support 1.3. 4G Turbo-V IP Release Information 1.4. 4G Turbo-V Performance and Resource Utilization
2. Getting Started with 4G Turbo-V IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 4G Turbo-V IP Timeout Behavior
3. Designing with the 4G Turbo-V Intel® FPGA IP x
3.1. Generating a 4G Turbo-V IP 3.2. Simulating the IP with the RTL Simulator 3.3. Simulating a 4G Turbo-V IP with MATLAB 3.4. Simulating a 4G Turbo-V IP with C-Models
4. 4G Turbo-V Intel® FPGA IP Functional Description x
4.1. 4G Turbo-V Downlink Accelerator 4.2. 4G Turbo-V Uplink Accelerator 4.3. 4G Turbo-V Signals and Interfaces
4.1. 4G Turbo-V Downlink Accelerator x
4.1.1. Turbo Encoder 4.1.2. Rate Matcher 4.1.3. Input and Output Data Formats 4.1.4. Latency Calculations 4.1.5. Throughput Calculations
4.2. 4G Turbo-V Uplink Accelerator x
4.2.1. Turbo Decoder 4.2.2. Input and Output Data Formats 4.2.3. Latency Calculations 4.2.4. Throughput Calculations
4.3. 4G Turbo-V Signals and Interfaces x
4.3.1. Avalon Streaming Interfaces in DSP Intel FPGA IP
1. About the 4G Turbo-V Intel® FPGA IP
2. Getting Started with 4G Turbo-V IP
3. Designing with the 4G Turbo-V Intel® FPGA IP
4. 4G Turbo-V Intel® FPGA IP Functional Description
5. 4G Turbo-V Intel FPGA IP User Guide Document Archive
6. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide

4. 4G Turbo-V Intel® FPGA IP Functional Description

The 4G Turbo-V Intel® FPGA IP comprises a downlink accelerator and an uplink accelerator.
Table 5.  LTE Block K SizeThe table shows codeblock size K valid values for LTE codeblock index idx
idx K idx K idx K idx K
1 40 48 416 95 1120 142 3200
2 48 49 424 96 1152 143 3264
3 56 50 432 97 1184 144 3328
4 64 51 440 98 1216 145 3392
5 72 52 448 99 1248 146 3456
6 80 53 456 100 1280 147 3520
7 88 54 464 101 1312 148 3584
8 96 55 472 102 1344 149 3648
9 104 56 480 103 1376 150 3712
10 112 57 488 104 1408 151 3776
11 120 58 496 105 1440 152 3840
12 128 59 504 106 1472 153 3904
13 136 60 512 107 1504 154 3968
14 144 61 528 108 1536 155 4032
15 152 62 544 109 1568 156 4096
16 160 63 560 110 1600 157 4160
17 168 64 576 111 1632 158 4224
18 176 65 592 112 1664 159 4288
19 184 66 608 113 1696 160 4352
20 192 67 624 114 1728 161 4416
21 200 68 640 115 1760 162 4480
22 208 69 656 116 1792 163 4544
23 216 70 672 117 1824 164 4608
24 224 71 688 118 1856 165 4672
25 232 72 704 119 1888 166 4736
26 240 73 720 120 1920 167 4800
27 248 74 736 121 1952 168 4864
28 256 75 752 122 1984 169 4928
29 264 76 768 123 2016 170 4992
30 272 77 784 124 2048 171 5056
31 280 78 800 125 2112 172 5120
32 288 79 816 126 2176 173 5184
33 296 80 832 127 2240 174 5248
34 304 81 848 128 2304 175 5312
35 312 82 864 129 2368 176 5376
36 320 83 880 130 2432 177 5440
37 328 84 896 131 2496 178 5504
38 336 85 912 132 2560 179 5568
39 344 86 928 133 2624 180 5632
40 352 87 944 134 2688 181 5696
41 360 88 960 135 2752 182 5760
42 368 89 976 136 2816 183 5824
43 376 90 992 137 2880 184 5888
44 384 91 1008 138 2944 185 5952
45 392 92 1024 139 3008 186 6016
46 400 93 1056 140 3072 187 6080
47 408 94 1088 141 3136 188 6144
Table 6.  DefinitionThe 4G Turbo-V IP uses these definitions.
Abbreviation Description
E Rate-matcher output block size
Nenc Number of parallel encoder engines
Ndec Number of parallel decoder engines
WLLR Bit width of input LLR
Wout Bit width of output data
I Number of full iterations, where each iteration consists of two half iterations.
Level Two Title