4G Turbo-V Intel® FPGA IP User Guide

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ID 683882
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 4G Turbo-V Intel® FPGA IP 2. Getting Started with 4G Turbo-V IP 3. Designing with the 4G Turbo-V Intel® FPGA IP 4. 4G Turbo-V Intel® FPGA IP Functional Description 5. 4G Turbo-V Intel FPGA IP User Guide Document Archive 6. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide
1. About the 4G Turbo-V Intel® FPGA IP x
1.1. 4G Turbo-V Intel® FPGA IP Features 1.2. 4G Turbo-V Intel® FPGA IP Device Family Support 1.3. 4G Turbo-V IP Release Information 1.4. 4G Turbo-V Performance and Resource Utilization
2. Getting Started with 4G Turbo-V IP x
2.1. Installing and Licensing Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. 4G Turbo-V IP Timeout Behavior
3. Designing with the 4G Turbo-V Intel® FPGA IP x
3.1. Generating a 4G Turbo-V IP 3.2. Simulating the IP with the RTL Simulator 3.3. Simulating a 4G Turbo-V IP with MATLAB 3.4. Simulating a 4G Turbo-V IP with C-Models
4. 4G Turbo-V Intel® FPGA IP Functional Description x
4.1. 4G Turbo-V Downlink Accelerator 4.2. 4G Turbo-V Uplink Accelerator 4.3. 4G Turbo-V Signals and Interfaces
4.1. 4G Turbo-V Downlink Accelerator x
4.1.1. Turbo Encoder 4.1.2. Rate Matcher 4.1.3. Input and Output Data Formats 4.1.4. Latency Calculations 4.1.5. Throughput Calculations
4.2. 4G Turbo-V Uplink Accelerator x
4.2.1. Turbo Decoder 4.2.2. Input and Output Data Formats 4.2.3. Latency Calculations Example 1: K = 6144, I = 8, Kπ= 6176 Example 2: K = 40, I = 8, Kπ= 64 4.2.4. Throughput Calculations
4.3. 4G Turbo-V Signals and Interfaces x
4.3.1. Avalon Streaming Interfaces in DSP Intel FPGA IP
1. About the 4G Turbo-V Intel® FPGA IP
2. Getting Started with 4G Turbo-V IP
3. Designing with the 4G Turbo-V Intel® FPGA IP
4. 4G Turbo-V Intel® FPGA IP Functional Description
5. 4G Turbo-V Intel FPGA IP User Guide Document Archive
6. Document Revision History for the 4G Turbo-V Intel® FPGA IP User Guide

4.2.3. Latency Calculations

The overall latency of the uplink accelerator is the sum of the latency of the subblock deinterleaver, the turbo decoder and the output. The IP reads and stores the input data into decoder’s input buffer, with de-interleaved memory write address.

The latency of the subblock deinterleaver is

L(subblock-deinterleaver) = Kπ+14.

Where this latency is measured from sink_sop to the time of the decoder starts to decode, when the IP was idle. The latency of turbo decoder depends on the block size (K), the number of full decoding iterations (I) to perform as follows

L(decoder) = 26 + (2 × f(K,Ndec) + 14) × 2 × I, when f(K, Ndec) <= 32

26 + (f(K, Ndec) + 46) × 2 × I, when f(K, Ndec) > 32

Where: I is the number of full decoding iterations and K is the block size.

f(K, Ndec) = K/4, if K <= 128;

K/8, if 128 < K <= 512;

K/16, otherwise.

L(output) = ceil(K/16) + 3

Example 1: K = 6144, I = 8, Kπ= 6176

L(deinterleaver) = 6176+14 = 6190 cycles

L(decoder) = 26 + (6144/16 + 46) × 2 × 8 = 6906 cycles

L(output) = ceil(6144/16)+3 = 387 cycles

L(uplink) = 6190 + 6906 + 387 = 13483 cycles

Example 2: K = 40, I = 8, Kπ= 64

L(deinterleaver) = 64+14 = 78 cycles

L(decoder) = 26 + (2*40/4 + 14) × 2 × 8 = 570 cycles

L(output) = ceil(40/16)+3 = 6 cycles

L(uplink) = 78 + 570 + 6 = 654 cycles

Level Two Title