4G Turbo-V Intel® FPGA IP User Guide

ID 683882
Date 4/01/2024
Public
Document Table of Contents

1.1. 4G Turbo-V Intel® FPGA IP Features

  • 3GPP LTE compliant with support for block sizes 40 to 6,144
  • C and MATLAB bit-accurate models.

The downlink accelerator includes:

  • Code block cyclic redundancy code (CRC) attachment
  • Turbo encoder
  • Rate matcher with:
    • Subblock interleaver
    • Bit collector
    • Bit selector
    • Bit pruner

The uplink accelerator includes:

  • Subblock deinterleaver
  • Turbo decoder with CRC check