4G Turbo-V Intel® FPGA IP User Guide

ID 683882
Date 4/01/2024
Public
Document Table of Contents

4.2.2. Input and Output Data Formats

Uplink accelerator data formats.
Table 11.  Input Data FormatThe uplink accelerator takes Kπ clock cycles and 3 LLRs per clock cycle, where input LLR bitwidth (WLLR ) = 8.
Input Order sink_data
3WLLR-1 down to 2WLLR 2WLLR-1 down to WLLR WLLR-1 down to 0
0 V0 (2) V0 (1) V0 (0)
1 V1 (2) V1 (1) V1 (0)
2 V2 (2) V2 (1) V2 (0)
Kπ-1 VKπ-1 (2) VKπ-1 (1) VKπ-1 (0)
Table 12.  Input Data FormatIn deinterleaver bypass mode, the uplink accelerator takes K+4 clock cycles and 3 LLRs per clock cycle, where input LLR bitwidth (WLLR ) = 8.
Input Order sink_data
3WLLR-1 down to 2WLLR 2WLLR-1 down to WLLR WLLR-1 down to 0
0 Z’0 Z0 X0
1 Z’1 Z1 X1
K-1 Z’K-1 ZK-1 XK-1
K XK+1 ZK XK
K+1 ZK+2 XK+2 ZK+1
K+2 X’K+1 Z’K X’K
K+3 Z’K+2 X’K+2 Z’K+1
Table 13.  Output Data FormatThe uplink accelerator outputs Wout=16 bits per clock cycle and the output block size is K
Output Order source_data
Wout down to 0
0 XWout-1, …,X2, X1,X0
1 X2Wout-1, …,XWout+2, XWout+1, XWout
K/Wout-1 XK-1, …,XK-Wout+2, XK-Wout+1, XK-Wout