4G Turbo-V Intel® FPGA IP User Guide

ID 683882
Date 4/01/2024
Public
Document Table of Contents

4.1.2. Rate Matcher

The rate matcher matches the number of bits in transport block to the number of bits that the IP transmits in that allocation. The input and output of the rate matcher is 24 bits wide. The IP defines the rate matching for Turbo coded transport channels for each code block. The rate matcher comprises: subblock interleaver, bit collector and bit selector.

The rate matcher sets up the subblock interleaver for each output stream from Turbo encoder. The streams include a message bit stream dk (0), 1st parity bit stream dk (1) and 2nd parity bit stream dk (2). Where

  • dk (0) = Xk
  • dk (1) = Zk
  • dk (2) = Z’k

for k= 0,1,2,…,K-1, and

  • dK (0) = XK, dK+1 (0) = ZK+1, dK+2 (0) = X’K, dK+3 (0) = Z’K+1
  • dK (1) = ZK, dK+1 (1) = XK+2, dK+2 (1) = Z’K, dK+3 (1) = X’K+2
  • dK (2) = XK+1, dK+1 (2) = ZK+2, dK+2 (2) = X’K+1, dK+3 (2) = Z’K+2

for the termination bits, when k = K, K+1 and K+2.

The input and output of the subblock interleaver is 24 bits wide. The bit collector combines the streams that come from the subblock interleaver and stores the output in a circular buffer. Bit selector selects a total of E bits from the circular buffer and outputs E bits with 24 bits per cycle.

Figure 6. Rate Matcher Block Diagram