4G Turbo-V Intel® FPGA IP User Guide

ID 683882
Date 4/01/2024
Public
Document Table of Contents

3.1. Generating a 4G Turbo-V IP

You can generate a downlink or uplink accelerator. To include the IP in a design, generate the IP in the Quartus® Prime software. Or optionally, you can generate a design example that includes the generated 4G Turbo-V IP, a C model, a MATLAB model, and simulation scripts. The software generates no hardware example in Generate Example Design.
  1. Create a New Quartus® Prime project
  2. Open IP Catalog.
  3. Select DSP > Error Detection and Correction > 4G Turbo-V and click Add
  4. Enter a name for your IP variant and click Create.
    The name is for both the top-level RTL module and the corresponding .ip file.
    The parameter editor for this IP appears.
  5. Choose Uplink or Downlink.
    Figure 3. 4G Turbo-V Parameters
  6. For an optional design example, click Generate Example Design

    No hardware example gets generated when you click Generate Example Design. If you upgrade the IP to a newer version, regenerate the example design.

    The software creates a design example and files that you can use for MATLAB, C, or RTL simulations.
  7. Click Generate HDL.
Quartus® Prime generates the RTL and the files necessary to instantiate the IP in your design and synthesize it.