1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

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ID 683876
Date 11/15/2021
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4.2. Timing Constraints

Constrain the PHY based on the fastest speed. For example, if you configure the PHY as 1G/2.5G, constrain it based on 2.5G.
Table 11.  Timing Constraints
PHY Configuration Constrain PHY for
2.5G 2.5G datapath
1G/2.5G 2.5G datapath
1G/2.5G/10G (MGBASE-T) 10G and 1G/2.5G datapath
10M/100M/1G/2.5G/5G/10G (USXGMII) 10G datapath
10M/100M/1G/2.5G 2.5G datapath
10M/100M/1G/2.5G/10G (SGMII/MGBASE-T) 10G and 1G/2.5G datapath

When you configure the PHY in 1G/2.5G/10G (MGBASE-T) configuration, Intel® recommends that you add the following constraints in the timing constraint file:

  • Set false path for the clocks used for the different speed so that the Timing Analyzer ignores paths for clocks that are in different groups. For example:
    set_clock_groups -physically_exclusive -group [get_clocks {DUT|CHANNEL_GEN[0].u_channel|phy|alt_mge_phy_0|profile0|*}] \
                                           -group [get_clocks {DUT|CHANNEL_GEN[0].u_channel|phy|alt_mge_phy_0|profile1|*}] \
                                           -group [get_clocks {DUT|CHANNEL_GEN[0].u_channel|phy|alt_mge_phy_0|profile2|*}]
    
    where profile0, profile1, and profile2 are created by the transceiver native PHY Synopsys Design Constraint (SDC) for 1G, 2.5G, and 10G clocks respectively.
  • Set false path from native PHY 10G clock to 1G/2.5G PHY logic and vice versa. Since the 1G/2.5G PHY logic is not running native PHY 10G clock, you do not need to ensure timing closure for the 1G/2.5G data path at 10G clock. For example:
    set_false_path -from [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile2|*}] \
                   -to [get_registers {*|alt_mge16_pcs_pma:*|*}]
    set_false_path -from [get_registers {*|alt_mge16_pcs_pma:*|*}] \
                   -to [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile2|*}]
    
    where the path indicated by profile2 is associated to the native PHY 10G clock, whereas the alt_mge16_pcs_pma path indicates the 1G/2.5G PHY logic.
  • Set false path from native PHY 1G and 2.5G clock to 10G PHY logic and vice versa. Since the 10G PHY logic is not running the native PHY 1G and 2.5G clocks, you do not need to ensure timing closure for the 10G data path at the native PHY 1G and 2.5G clocks. For example:
    set_false_path -from [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile0|* \
                                      DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile1|*}] \
                   -to [get_registers *|alt_mge_phy_xgmii_pcs:*|*]
    set_false_path -from [get_registers *|alt_mge_phy_xgmii_pcs:*|*] \
                   -to [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile0|* \
                                    DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile1|*}]
    
    where the paths indicated by profile0 and profile1 are associated to the native PHY 1G and 2.5G clocks respectively, whereas the alt_mge_phy_xgmii_pcs path indicates the 10G PHY logic.

When you configure the PHY in 1G/2.5G configuration, Intel® recommends that you add the following constraint in the timing constraint file:

  • Set false path for the clocks used for the different speed so that the Timing Analyzer ignores paths for clocks that are in different groups. For example:
    set_clock_groups -physically_exclusive -group [get_clocks {DUT|CHANNEL_GEN[0].u_channel|phy|alt_mge_phy_0|profile0|*}] \
                                           -group [get_clocks {DUT|CHANNEL_GEN[0].u_channel|phy|alt_mge_phy_0|profile1|*}] 
    
    where profile0 and profile1 are created by the transceiver native PHY SDC for the 1G and 2.5G clocks respectively.

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