1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

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ID 683876
Date 11/15/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Integrating Your IP Core in Your Design x
2.4.1. Pin Assignments 2.4.2. Adding the Transceiver PLL 2.4.3. Adding the Intel® Stratix® 10 Transceiver PHY Reset Controller
4. Functional Description x
4.1. Clocking and Reset Sequence 4.2. Timing Constraints 4.3. Switching Operation Speed
5. Configuration Registers x
5.1. Register Map 5.2. Register Definitions
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Transceiver Mode and Operating Speed Signals 6.3. Serial Interface Signals 6.4. GMII Signals 6.5. XGMII Signals 6.6. Avalon® -MM Interface Signals 6.7. Transceiver Status and Reconfiguration Signals 6.8. Status Signals
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives
A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

6.8. Status Signals

Table 23.  Status Signals
Signal Name Direction Clock Domain Width Description PHY Configurations
led_char_err Output Synchronous to rx_clkout 1 Asserted when a 10-bit character error is detected in the RX data. This signal is not applicable for 10GbE.
  • 2.5G
  • 1G/2.5G
  • 10M/100M/1G/2.5G
  • 1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G/10G (MGBASE-T)
led_link Output Synchronous to tx_clkout 1 Asserted when the link synchronization for 1GbE or 2.5GbE is successful. This signal is not applicable for 10GbE.
led_disp_err Output Synchronous to rx_clkout 1 Asserted when a 10-bit running disparity error is detected in the RX data. A running disparity error indicates that more than the previous and perhaps the current received group had an error. This signal is not applicable for 10GbE.
led_an Output Synchronous to rx_clkout 1 Asserted when auto-negotiation is completed. This signal is not applicable for 10GbE. All
led_panel_link Output Synchronous to rx_clkout 1 When asserted, this signal indicates the following behavior:
Mode Behavior
1000 Base-X without Auto-negotiation When asserted, indicates successful link synchronization.
SGMII mode without Auto-negotiation When asserted, indicates successful link synchronization.
1000 Base-X with Auto-negotiation Clause 37 Auto-negotiation status. The PCS function asserts this signal when auto-negotiation completes.
SGMII mode with MAC mode Auto-negotiation Clause 37 Auto-negotiation status. The PCS function asserts this signal when auto-negotiation completes.
This signal is applicable only when SGMII 10M/100M mode is enabled.
  • 10M/100M/1G/2.5G
  • 10M/100M/1G/2.5G/10G (MGBASE-T)
rx_block_lock Output Synchronous to rx_clkout 1 Asserted when the link synchronization for 10GbE of MGBASE-T and all speeds of USXGMII is successful.
  • 1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
The latency indicators are connected from PHY to MAC block, where the MAC block uses them to calculate timestamp of the transmitted or received packets. For more information, refer to Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide.
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