1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

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ID 683876
Date 11/15/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Integrating Your IP Core in Your Design x
2.4.1. Pin Assignments 2.4.2. Adding the Transceiver PLL 2.4.3. Adding the Intel® Stratix® 10 Transceiver PHY Reset Controller
4. Functional Description x
4.1. Clocking and Reset Sequence 4.2. Timing Constraints 4.3. Switching Operation Speed
5. Configuration Registers x
5.1. Register Map 5.2. Register Definitions
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Transceiver Mode and Operating Speed Signals 6.3. Serial Interface Signals 6.4. GMII Signals 6.5. XGMII Signals 6.6. Avalon® -MM Interface Signals 6.7. Transceiver Status and Reconfiguration Signals 6.8. Status Signals
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives
A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

Document Version Intel® Quartus® Prime Version Changes
2021.11.15 19.1 Updated Support Level in Device Family Support topic.
2019.05.10 19.1
  • Renamed Altera Debug Master Endpoint (ADME) to Native PHY Debug Master Endpoint (NPDME).
  • Updated the Clocking and Reset Sequence topic to state that the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core for Intel® Stratix® 10 devices supports up to ±100 ppm clock frequency difference for a maximum packet length of 16,000 bytes.
2019.01.30 18.0 Updated Table: Clock and Reset Signals to update the description for rx_pma_clkout.
2018.09.24 18.0
  • Updated the note in About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core topic.
  • Updated Table: Status Signals to include a Clock Domain column.
  • Updated the Functional Description topic.
  • Updated the Timing Constraints topic.
  • Updated Table: XGMII Signals:
    • Corrected the direction of xgmii_tx_valid.
    • Updated the toggle rate of 10G speed for xgmii_tx_valid and xgmii_rx_valid.
  • Renamed topic title Register Access to Register Definitions.
  • Made minor editorial edits.
2018.05.07 18.0
  • Renamed the document as 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel Stratix 10 FPGA IP User Guide.
  • Renamed "1G/2.5G/5G/10G Multi-rate Ethernet PHY" IP core to "1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP" as per Intel rebranding.
  • Added support for the following variants:
    • 10M/100M/1G/2.5G/5G/10G (USXGMII)
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) with IEEE 1588v2
  • Updated topic title Datasheet to About 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP.
  • Updated the About 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP topic.
  • Updated Table: 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core Features.
  • Updated Table: Resource Utilization:
    • Updated the resource utilization for all configurations.
    • Added resource utilization information for 10M/100M/1G/2.5G/5G/10G (USXGMII) with IEEE 1588v2 configuration.
  • Removed a note from the Specifying the IP Core Parameters and Options topic.
  • Updated Table: Slowest Supported Device Speed Grades with supported speed grade for 10M/100M/1G/2.5G/5G/10G (USXGMII) with 1588 feature.
  • Updated Figure: IP Parameter Editor.
  • Updated Table: 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core Parameters:
    • Updated descriptions for Connect to MGBASE-T PHY, Connect to NBASE-T PHY, Enable IEEE 1588 Precision Time Protocol, PHY ID (32 bit), and Reference clock frequency for 10 GbE (MHz) parameters.
    • Updated options for Speed parameter.
  • Updated the Functional Description topic.
  • Updated the Clocking and Reset Sequence topic.
  • Updated Table: Timing Constraints to include 10M/100M/1G/2.5G and 10M/100M/1G/2.5G/10G (SGMII/MGBASE-T) configurations.
  • Renamed topic title Register Definitions to Register Access.
  • Updated Table: PHY Registers Definition:
    • Updated the description for Bit [4:2]: USXGMII_SPEED of the usxgmii_control signal.
    • Updated the description for link_timer signal.
  • Updated Figure: Interface Signals.
  • Updated Tables: Clock and Reset Signals, GMII Signals, and XGMII Signals.
  • Updated for latest Intel branding standards.
  • Made editorial updates throughout the document.
Date Version Changes
November 2017 2017.11.06
  • Changed the document title from Intel® Stratix® 10 Multi-rate Ethernet PHY IP Core User Guide to Intel® Stratix® 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core User Guide.
  • Added support for the 1G/2.5G/5G/10G (USXGMII) variant.
  • Added new Table: Slowest Supported Device Speed Grades to include speed grade support.
  • Added resource utilization for 1G/2.5G/5G/10G (USXGMII) configuration.
  • Added new chapter Getting Started explaining how to install, generate and integrate IP core in your design.
  • Added information in Clocking and Reset Sequence to confirm that the Intel® Stratix® 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP core can handle clock frequency difference up to ±100 ppm.
  • Added the PHY configuration information in Interface Signals section.
June 2017 2017.06.05
  • Added the SGMII (10M/100M/1G) support for 1G/2.5G and 1G/2.5/10G (MGBASE-T).
  • Added resource utilization for 1G/2.5G with IEEE 1588v2 enabled, 10M/100M/1G/2.5G, and 10M/100M/1G/2.5G/10G configurations.
  • Added the Enable SGMII bridge parameter and removed the Enable ODI acceleration logic parameter in the Table: 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core Parameters.
  • Updated the Table: Supported Operating Speed with SGMII mode information.
  • Added registers for SGMII mode (see address 0x05 (SGMII mode) and 0x14).
  • Added the following signals:
    • tx_clkena and rx_clkena in Table: GMII Signals.
    • led_panel_link in Table: Status Signals.
May 2017 2017.05.08 Initial release.
Level Two Title