1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

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ID 683876
Date 11/15/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Integrating Your IP Core in Your Design x
2.4.1. Pin Assignments 2.4.2. Adding the Transceiver PLL 2.4.3. Adding the Intel® Stratix® 10 Transceiver PHY Reset Controller
4. Functional Description x
4.1. Clocking and Reset Sequence 4.2. Timing Constraints 4.3. Switching Operation Speed
5. Configuration Registers x
5.1. Register Map 5.2. Register Definitions
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Transceiver Mode and Operating Speed Signals 6.3. Serial Interface Signals 6.4. GMII Signals 6.5. XGMII Signals 6.6. Avalon® -MM Interface Signals 6.7. Transceiver Status and Reconfiguration Signals 6.8. Status Signals
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives
A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

6.1. Clock and Reset Signals

Table 16.  Clock and Reset Signals
Signal Name Direction Width Description PHY Configurations
Clock signals  
tx_clkout Output 1 GMII TX clock, derived from tx_serial_clk[1:0]. Provides 156.25 MHz timing reference for 2.5GbE; 62.5 MHz for 1GbE; 6.25 MHz for 100M; 0.625 MHz for 10M.
  • 2.5G
  • 1G/2.5G
  • 10M/100M/1G,2.5G
  • 1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G/10G (MGBASE-T)
rx_clkout Output 1 GMII RX clock, derived from tx_serial_clk[1:0]. Provides 156.25 MHz timing reference for 2.5GbE; 62.5 MHz for 1GbE; 6.25 MHz for 100M; 0.625 MHz for 10M.
  • 2.5G
  • 1G/2.5G
  • 10M/100M/1G/2.5G
  • 1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G/10G (MGBASE-T)
csr_clk Input 1 Clock for the Avalon® -MM control and status interface. Intel recommends 125 – 156.25 MHz for this clock. All
xgmii_tx_coreclkin Input 1 XGMII TX clock. Provides 156.25 MHz timing reference for 10GbE and 312.5 MHz for 10M/100M/1G/2.5G/5G/10G (USXGMII) mode. Synchronous to tx_serial_clk with zero ppm.
  • 1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
xgmii_rx_coreclkin Input 1 XGMII RX clock. Provides 156.25 MHz timing reference for 10GbE and 312.5 MHz for 10M/100M/1G/2.5G/5G/10G (USXGMII) mode.
  • 1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
latency_measure_clk Input 1 Sampling clock for measuring the latency of the 16-bit GMII datapath. This clock operates at 80 MHz and is available only when the IEEE 1588v2 feature is enabled.
  • 2.5G
  • 1G/2.5G
  • 1G/2.5G/10G (MGBASE-T) with IEEE 1588v2 feature
latency_sclk Input 1 Sampling clock for measuring the latency of the transceiver AIB datapath. The clock period is 6.5 ns. It is available only when the IEEE 1588v2 feature is enabled.
  • 2.5G
  • 1G/2.5G
  • 1G/2.5G/10G (MGBASE-T) with IEEE 1588v2 feature
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
Serial interface clock signals
tx_serial_clk Input 1-3 Serial clock from transceiver PLLs.
  • 2.5GbE: Connect bit [0] to the transceiver PLL. This clock operates at 1562.5 MHz.
  • 1GbE: Connect bit [1] to the transceiver PLL. This clock operates at 625 MHz.
  • 10GbE: Connect bit [2] to the transceiver PLL. This clock operates at 5156.25 MHz.
  • 10M/100M/1G/2.5G/5G/10G (USXGMII) mode: Connect bit [0] to 5156.25 MHz.
All
rx_cdr_refclk

Input

1

125-MHz RX CDR reference clock for 1GbE and 2.5GbE

  • 2.5G
  • 1G/2.5G, 10M/100M/1G/2.5G
  • 1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G/10G (MGBASE-T)
rx_cdr_refclk_1 Input 1 RX CDR reference clock for 10G of 1G/2.5G/10G (MGBASE-T) and all speeds of USXGMII. The frequency of this clock can be either 322.265625 MHz or 644.53125 MHz, as specified by the Reference clock frequency for 10 GbE (MHz) parameter setting.
  • 1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
rx_pma_clkout Output 1 Recovered clock from CDR, operates at the following frequency:
10M/100M/1G/2.5G/5G/10G (USXGMII) speed mode:
  • All speeds: 156.25 MHz
Other speed modes:
  • 1GbE: 125 MHz
  • 2.5GbE: 312.5 MHz
  • 10GbE: 156.25 MHz
 All
Reset signals
reset Input 1 Active-high global reset. Assert this signal to trigger an asynchronous global reset. All
tx_analogreset Input 1 Connect this signal to the Transceiver PHY Reset Controller IP core. When asserted, triggers an asynchronous reset to the analog block on the TX path. All
tx_analogreset_stat Output 1 Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device. All
tx_digitalreset Input 1 Connect this signal to the Transceiver PHY Reset Controller IP core. When asserted, triggers an asynchronous reset to the digital logic on the TX path. All
tx_digitalreset_stat Output 1 Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device. All
rx_analogreset Input 1 Connect this signal to the Transceiver PHY Reset Controller IP core. When asserted, triggers an asynchronous reset to the receiver CDR. All
rx_analogreset_stat Output 1 Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device. All
rx_digitalreset Input 1

Connect this signal to the Transceiver PHY Reset Controller IP core. When asserted, triggers an asynchronous reset to the digital logic on the RX path.

All
rx_digitalreset_stat Output 1 Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device. All
Level Two Title