1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

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ID 683876
Date 11/15/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Integrating Your IP Core in Your Design x
2.4.1. Pin Assignments 2.4.2. Adding the Transceiver PLL 2.4.3. Adding the Intel® Stratix® 10 Transceiver PHY Reset Controller
4. Functional Description x
4.1. Clocking and Reset Sequence 4.2. Timing Constraints 4.3. Switching Operation Speed
5. Configuration Registers x
5.1. Register Map 5.2. Register Definitions
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Transceiver Mode and Operating Speed Signals 6.3. Serial Interface Signals 6.4. GMII Signals 6.5. XGMII Signals 6.6. Avalon® -MM Interface Signals 6.7. Transceiver Status and Reconfiguration Signals 6.8. Status Signals
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives
A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

6.6. Avalon® -MM Interface Signals

The Avalon® -MM interface is an Avalon® -MM slave port. This interface uses word addressing and provides access to the 16-bit configuration registers of the PHY. The following signals are synchronous to csr_clk.

Table 21.   Avalon® -MM Interface Signals
Signal Name Direction Width Description PHY Configurations
csr_address Input 5, 11 Use this bus to specify the register address to read from or write to. The width is:
  • 5 bits for 2.5G and 1G/2.5G configurations.
  • 11 bits for 1G/2.5G/10G (MGBASE-T) and 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.
All
csr_read Input 1 Assert this signal to request a read operation.
csr_readdata Output 16, 32 Data read from the specified register. The data is valid only when the csr_waitrequest signal is deasserted. The width is:
  • 16 bits for 2.5G and 1G/2.5G configurations.
  • 32 bits for 1G/2.5G/10G (MGBASE-T) and 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations. The upper 16 bits are reserved.
csr_write Input 1 Assert this signal to request a write operation.
csr_writedata Input 16, 32 Data to be written to the specified register. The data is written only when the csr_waitrequest signal is deasserted. The width is:
  • 16 bits for 2.5G and 1G/2.5G configurations.
  • 32 bits for 1G/2.5G/10G (MGBASE-T) and 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations. The upper 16 bits are reserved.
csr_waitrequest Output 1 When asserted, indicates that the PHY is busy and not ready to accept any read or write requests.
  • When you have requested for a read or write, keep the control signals to the Avalon® -MM interface constant while this signal is asserted. The request is complete when it is deasserted.
  • This signal can be high or low during idle cycles and reset. Therefore, the user application must not make any assumption of its assertion state during these periods.
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