1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

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ID 683876
Date 11/15/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Integrating Your IP Core in Your Design x
2.4.1. Pin Assignments 2.4.2. Adding the Transceiver PLL 2.4.3. Adding the Intel® Stratix® 10 Transceiver PHY Reset Controller
4. Functional Description x
4.1. Clocking and Reset Sequence 4.2. Timing Constraints 4.3. Switching Operation Speed
5. Configuration Registers x
5.1. Register Map 5.2. Register Definitions
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Transceiver Mode and Operating Speed Signals 6.3. Serial Interface Signals 6.4. GMII Signals 6.5. XGMII Signals 6.6. Avalon® -MM Interface Signals 6.7. Transceiver Status and Reconfiguration Signals 6.8. Status Signals
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives
A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

6.4. GMII Signals

The 16-bit TX and RX GMII supports 1GbE and 2.5GbE at 62.5 MHz and 156.25 MHz respectively.
Table 19.  GMII Signals
Signal Name Direction Width Description PHY Configurations
TX GMII signals — synchronous to tx_clkout
gmii16b_tx_d Input 16 TX data from the MAC. The MAC sends the lower byte first followed by the upper byte.
  • 2.5G
  • 1G/2.5G
  • 10M/100M/1G/2.5G
  • 1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G/10G (MGBASE-T)
gmii16b_tx_en Input 2 When asserted, indicates the start of a new frame from the MAC. Bit[0] corresponds to gmii16b_tx_d[7:0]; bit[1] corresponds to gmii16b_tx_d[15:8].

This signal remains asserted until the PHY receives the last byte of the data frame.

gmii16b_tx_err Input 2 When asserted, indicates an error. Bit[0] corresponds to gmii16b_tx_err[7:0]; bit[1] corresponds to gmii16b_tx_err[15:8].

The bits can be asserted at any time during a frame transfer to indicate an error in the current frame.

gmii16b_tx_latency Output 22 The latency of the PHY excluding the PMA block on the TX datapath:
  • Bits [21:10]: The number of clock cycles.
  • Bits [9:0]: The fractional number of clock cycles.

This signal is available when only the Enable IEEE 1588 Precision Time Protocol parameter is selected.

  • 2.5G
  • 1G/2.5G with IEEE 1588v2 feature
  • 1G/2.5G/10G (MGBASE-T) with IEEE 1588v2 feature
tx_clkena Output 1 TX clock enable for SGMII 10M/100M operating speeds. In 1 Gbps mode, this signal is always asserted; in 100 Mbps mode, this signal is asserted once every 10 clock cycles; in 10 Mbps mode, this signal is asserted once every 100 clock cycles.

For 100M mode, tx_clkout is divided to 6.25 MHz.

For 10M mode, tx_clkout is divided to 0.625 MHz.

This signal is available when only the Enable SGMII bridge parameter is selected.

  • 10M/100M/1G/2.5G
  • 10M/100M/1G/2.5G/10G (MGBASE-T)
RX GMII signals — synchronous to rx_clkout
gmii16b_rx_d Output 16 RX data to the MAC. The PHY sends the lower byte first followed by the upper byte. Rate matching is done by the PHY on the RX data from the RX recovered clock to rx_clkout.
  • 2.5G
  • 1G/2.5G
  • 10M/100M/1G/2.5G
  • 1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G/10G(MGBASE-T)
gmii16b_rx_err Output 2 When asserted, indicates an error. Bit[0] corresponds to gmii16b_rx_err[7:0]; bit[1] corresponds to gmii16b_rx_err[15:8].

The bits can be asserted at any time during a frame transfer to indicate an error in the current frame.

gmii16b_rx_dv Output 2 When asserted, indicates the start of a new frame. Bit[0] corresponds to gmii16b_rx_d[7:0]; bit[1] corresponds to gmii16b_rx_d[15:8].

This signal remains asserted until the PHY sends the last byte of the data frame.

gmii16b_rx_latency Output 22 The latency of the PHY excluding the PMA block on the RX datapath:
  • Bits [21:10]: The number of clock cycles.
  • Bits [9:0]: The fractional number of clock cycles.

This signal is available only when the Enable IEEE 1588 Precision Time Protocol parameter is selected.

  • 2.5G
  • 1G/2.5G with IEEE 1588v2 feature
  • 1G/2.5G/10G (MGBASE-T) with IEEE 1588v2 feature
rx_clkena Output 1 RX clock enable for SGMII 10M/100M operating speeds. In 1 Gbps mode, this signal is always asserted; in 100Mbps mode, this signal is asserted once every 10 clock cycles; in 10 Mbps mode, this signal is asserted once every 100 clock cycles.

For 100M mode, rx_clkout is divided to 6.25 MHz.

For 10M mode, rx_clkout is divided to 0.625 MHz.

This signal is available when only the Enable SGMII bridge parameter is selected.

  • 10M/100M/1G/2.5G
  • 10M/100M/1G/2.5G/10G (MGBASE-T)
Level Two Title