1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

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ID 683876
Date 11/15/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Integrating Your IP Core in Your Design x
2.4.1. Pin Assignments 2.4.2. Adding the Transceiver PLL 2.4.3. Adding the Intel® Stratix® 10 Transceiver PHY Reset Controller
4. Functional Description x
4.1. Clocking and Reset Sequence 4.2. Timing Constraints 4.3. Switching Operation Speed
5. Configuration Registers x
5.1. Register Map 5.2. Register Definitions
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Transceiver Mode and Operating Speed Signals 6.3. Serial Interface Signals 6.4. GMII Signals 6.5. XGMII Signals 6.6. Avalon® -MM Interface Signals 6.7. Transceiver Status and Reconfiguration Signals 6.8. Status Signals
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives
A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

4. Functional Description

The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core for Intel® Stratix® 10 devices implements the 10M to 10Gbps Ethernet PHY in accordance with the IEEE 802.3 Ethernet Standard. This IP core handles the frame encapsulation and flow of data between a client logic and Ethernet network via a 10M to 10GbE PCS and PMA (PHY). You can use the Native PHY IP core to configure the transceiver PHY for your protocol implementation. Refer to the Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide for more information on using the Native PHY IP core.

Figure 5. Architecture of 2.5G, 1G/2.5G, 10M/100M/1G/2.5G, 1G/2.5G/10G, 10M/100M/1G/2.5G/10G (MGBASE-T) Configuration
In the transmit direction, the PHY encodes the Ethernet frame as required for reliable transmission over the media to the remote end. In the receive direction, the PHY passes frames to the MAC.
Note: You can generate the MAC and PHY design example using the Low Latency Ethernet 10G MAC Intel® FPGA IP Parameter Editor.
The IP core includes the following interfaces:
  • Datapath client-interface:
    • 10GbE—XGMII, 64 bits
    • 10M/100M/1G/2.5GbE—GMII, 16 bit
    • 10M/100M/1G/2.5G/5G/10G (USXGMII)—XGMII, 32 bits

    For 1G/2.5/10G (MGBASE-T), select an interface based on the respective operating speed.

  • Management interface— Avalon® -MM host slave interface for PHY management.
  • Datapath Ethernet interface with the following available options:
    • 10GbE—Single 10.3125 Gbps serial link
    • 2.5GbE—Single 3.125 Gbps serial link
    • 10M/100M/1GbE—Single 1.25 Gbps SGMII serial link
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) —Single 10.3125 Gbps serial link

    For 1G/2.5/10G (MGBASE-T), select an ethernet interface based on the respective operating speed.

  • Transceiver PHY dynamic reconfiguration interface—an Avalon® -MM interface to read and write the Intel® Stratix® 10 Native PHY IP core registers. This interface supports dynamic reconfiguration of the transceiver. It is used to configure the transceiver operating modes to switch to desired Ethernet operating speeds.
Figure 6. Architecture of 10M/100M/1G/2.5G/5G/10G (USXGMII) Configuration
The 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration supports the following features:
  • USXGMII—10M/100M/1G/2.5G/5G/10G speeds
  • Full duplex data transmission
  • USXGMII Auto-Negotiation
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