1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

ID 683876
Date 11/15/2021
Public
Document Table of Contents

2.4.2. Adding the Transceiver PLL

1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core requires an external PLL to drive TX serial clock, in order to compile and to function corrrectly in hardware. You must instantiate and connect ATX PLL/fPLL IP core to the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP core.

You can create an external transceiver PLL from the IP Catalog. Select the Intel® Stratix® 10 L-Tile/H-Tile Transceiver ATX PLL core or Intel® Stratix® 10 L-Tile/H-Tile fPLL core.

Table 9.  Instantiate TX PLL
Speed Reference Clock Frequency (MHz) PLL Output Clock (MHz)
1G 125 625
2.5G 125 1562.5
10G 644.53125/322.265625 5156.25