1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

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ID 683876
Date 11/15/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Integrating Your IP Core in Your Design x
2.4.1. Pin Assignments 2.4.2. Adding the Transceiver PLL 2.4.3. Adding the Intel® Stratix® 10 Transceiver PHY Reset Controller
4. Functional Description x
4.1. Clocking and Reset Sequence 4.2. Timing Constraints 4.3. Switching Operation Speed
5. Configuration Registers x
5.1. Register Map 5.2. Register Definitions
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Transceiver Mode and Operating Speed Signals 6.3. Serial Interface Signals 6.4. GMII Signals 6.5. XGMII Signals 6.6. Avalon® -MM Interface Signals 6.7. Transceiver Status and Reconfiguration Signals 6.8. Status Signals
1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide Archives
A. Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

1.1. Features

Table 1.   1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core Features
Feature Description
Operating speeds 10M, 100M, 1G, 2.5G, 5G, and 10G.
MAC-side interface 16-bit GMII for 10M/100M/1G/2.5G (MGBASE-T).
32-bit XGMII for 10M/100M/1G/2.5G/5G/10G (USXGMII/NBASE-T).
64-bit XGMII for 10G (MGBASE-T).
Network-side interface 1.25 Gbps for 1G (MGBASE-T) and 10M/100M/1G (SGMII).
3.125 Gbps for 2.5G (MGBASE-T).
10.3125 Gbps for 10M/100M/1G/2.5G/5G/10G (USXGMII/NBASE-T) and 10G (MGBASE-T).
Avalon® Memory-Mapped ( Avalon® -MM) interface Provides access to the configuration registers of the PHY.
Physical Coding Sublayer (PCS) function 1000BASE-X for 1G and 2.5G.
10GBASE-R for 10G.
USXGMII PCS for 10M/100M/1G/2.5G/5G/10G (USXGMII).
SGMII (10M/100M/1G) for 1G/2.5 and 1G/2.5/10G (MGBASE-T).
Auto-negotiation

Implements IEEE 802.3 clause 37. Supported in 1GbE only.

USXGMII Auto-negotiation supported in the 10M/100M/1G/2.5G/5G/10G (USXGMII/NBASE-T) configuration.

SGMII Auto-negotiation supported in the 10M/100M/1G (SGMII) configuration.

IEEE 1588v2 Provides the required latency to the MAC if the MAC enables the IEEE 1588v2 feature.
Supported:
  • 2.5G
  • 1G/2.5G
  • 1G/2.5G/10G (MGBASE-T)
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
    Note: For the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration, the provided latency is applicable only for 100M, 1G, 2.5G, 5G, and 10G modes.
Not Supported:
  • 10M/100M/1G/2.5G
  • 10M/100M/1G/2.5G/10G (MGBASE-T)
Sync-E Provides the clock for Sync-E implementation.
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