1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP User Guide

ID 683876
Date 11/15/2021
Public
Document Table of Contents

2.4.3. Adding the Intel® Stratix® 10 Transceiver PHY Reset Controller

You must add an Intel® Stratix® 10 Transceiver PHY Reset Controller IP core to your design, and connect it to the 1G/2.5/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core reset signals. This block implements a reset sequence that resets the device transceiver correctly.

You can use the IP Catalog to create a transceiver PHY reset controller.