3.4. Signal and Port Reference
The following section describes all F-Tile PMA/FEC Direct PHY Intel® FPGA IP ports and signals.
Each tx_parallel_data and rx_parallel_data bus is exposed as 80 to 320 bits. Some bits map to special functionality.
Each PMA channel transmits and receives 80 to 320 bits, parallel data interface. The determination of active and inactive ports depends on specific configuration parameters, such as the number of lanes and the PMA width.
For details about mapping of data and control signals, refer to Parallel Data Mapping Information.
When you enable the Provide separate interface for each PMA option for the F-Tile PMA/FEC Direct PHY Intel® FPGA IP, the PHY presents separate data and clock interfaces for each PMA lane, rather than a wide bus. Each PMA lane signal name is appended with a _xcvr<n> suffix, with n = PMA index number. When Provide separate interface for each PMA is disabled, the signal name does not append _xcvr<n>.
For example, if you enable Provide separate interface for each PMA for two PMA lane configuration, the serial port signal names appear as:
If you disable Provide separate interface for each PMA for two lane PMA configuration, the serial port signal name appears as: tx_serial_data[1:0].
The following are the signals that do not have separate interfaces when Provide separate interface for each PMA option is on:
- system_pll_clk_link, rx_cdr_divclk_link0, rx_cdr_divclk_link1
- tx_reset, rx_reset, tx_reset_ack, rx_reset_ack, tx_ready, rx_ready
- rsfec signals
- tx_cadence, tx_cadence_fast_clk, tx_cadence_slow_clk, tx_cadence_slow_clk_locked
- Reconfiguration Avalon® memory-mapped interface ports
- rx_cdr_divclk_link0, and rx_cdr_divclk_link1
FGT: 1, 2, 4, 6, 8, 12, 16
FHT: 1, 2, 4
|N is the number of PMA lanes.|
|<n>||0 to N-1||n is the PMA index number.|
PMA width = 8, 10, 16, 20, and 32-bit, X=1
PMA width = 64-bit, X=2
PMA width = 128-bit, X=4
|X is the number of streams.|
|<K p >||
K p = 0,1,2,3,3,4,4 for N = 1,2,4,6,8,12,16
K p is the PMA reconfiguration interface address.
K p =0 if separate Avalon® interface per PMA is enabled
K p =Ceiling(log2(N) if separate Avalon® interface per PMA is disabled.
K d = 0,1,2,3,3,4,4 for N = 1,2,4,6,8,12,16
| K d is the datapath reconfiguration interface address.
K d =0 if a separate Avalon® interface per PMA is enabled or FEC is enabled.
K d =Ceiling(log2(N) if separate Avalon® interface per PMA is disabled and FEC is disabled.
If PMA width = 8, 10, 16, 20, or 32-bit, then D = PMA Width
If PMA width = 64 or 128-bit, then D = 32
|D is the data width value to calculate the total parallel data bits.|