5.2.1. Setting General and Common Datapath Options
The following parameter values define an instance of F-Tile PMA/FEC Direct PHY Intel® FPGA IP with the following properties:
- Two FGT PMA operating at duplex mode, NRZ modulation, 32-bit data width
- Two PMA lanes with data rate at 25.78125Gbps (supports 51.5625Gbps link)
- System PLL datapath clocking mode and the output frequency
|Number of PMA lanes||2|
|FGT PMA configuration rules||Basic|
|PMA modulation type||NRZ|
This parameterization uses two FGT PMA lanes. There are two EMIB, connecting to two PMA lanes, to form two streams of PMA direct datapath. The following is the bonding configuration for this example:
- PMA bonding is disabled because the PMA width is 32-bit.
- System bonding is enabled so two PMA lanes bond to form the 51.625Gbps link.
400G Hard IP Fracture Resources Used and Placed by the Design shows the assignment of the PMA physical lanes to FGT3_Quad3 and FGT2_Quad3 location. This physical location of the PMA lanes uses the resources highlighted in (light blue) in the diagram. These resources are:
- PMA lanes placed in FGT3_Quad3 and FGT2_Quad3
- Fracture st_x1_0 and st_x1_1
- EMIB_23 and EMIB_22