Visible to Intel only — GUID: zre1628213998589
Ixiasoft
Visible to Intel only — GUID: zre1628213998589
Ixiasoft
3.14.2.2. FGT Attribute Access Method
- Write data value to LINK_MNG_SIDE_CPI_REGS register to assert a service request.
- Read PHY_SIDE_CPI_REGS register to confirm the request has been acknowledged and completed; if not, repeat this step.
- Write data value to LINK_MNG_SIDE_CPI_REGS register to deassert the service request.
- Read PHY_SIDE_CPI_REGS register to confirm the request in step 3 has been acknowledged; if not, repeat this step.
Channels | LINK_MNG_SIDE_CPI_REGS Address | PHY_SIDE_CPI_REGS Address |
---|---|---|
Channel 0 or 1 or 2 or 3 | 0x0009003c | 0x00090040 |
Channel 4 or 5 or 6 or 7 | 0x0049003c | 0x00490040 |
Channel 8 or 9 or 10 or 11 | 0x0089003c | 0x00890040 |
Channel 12 or 13 or 14 or 15 | 0x00C9003c | 0x00C90040 |
Serial Loopback | TX and RX PRBS Selection | Polarity Setup | BER Measurement | Start/Stop Test | |
---|---|---|---|---|---|
Data field[31:16] | Enable: 0x6 Disable: 0x0 |
PRBS7: 0x208 PRBS9: 0x249 PRBS11: 0x28A PRBS13: 0x965 PRBS23: 0x2CB PRBS31: 0x30C QPRBS13: 0x34D PRBS13Q: 0x820 PRBS31Q: 0x861 SSPR: 0x8A2 SSPR1: 0x8E3 SSPRQ: 0x924 |
Reverse: 0x1 Revert back: 0x0 |
0x14 | Start: 0x20 Stop: 0x21 |
Option field [15:12] | Bit [15] SERVICE_REQ to indicate a request: 0 = no request, 1 = service requested. Bit [14] RESET: 0 = not in reset, 1 = in reset. Bit [13] SET_GET: 0 = GET parameters, 1 = SET parameters. Bit [12]: reserved |
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Lane number field[11:8] | Use 0xFFFFC[1:0], 0x1FFFFC[1:0]… 0xFFFFFC[1:0] to read back logical lane 0, 1 until lane 15’s physical lane number.
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Opcode field[7:0] | 0x40 | 0x41 | TX polarity: 0x65 RX polarity: 0x66 |
0x45 | 0x0F
Note: 0x0F is not equivalent to 0xF
|
Get Status | Error Number to Inject | Enable Error Injection | Read Results | Finish BER Measurement | |
---|---|---|---|---|---|
Data field[31:16] | 0x0 |
0x[Error_Num] |
0x23 |
0x0 |
0x0 |
Option field [15:12] | Bit [15] SERVICE_REQ to indicate a request: 0 = no request, 1 = service requested. Bit [14] RESET: 0 = not in reset, 1 = in reset. Bit [13] SET_GET: 0 = GET parameters, 1 = SET parameters. Bit [12]: reserved |
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Lane number field[11:8] | Use 0xFFFFC[1:0], 0x1FFFFC[1:0]… 0xFFFFFC[1:0] to read back logical lane 0, 1 until lane 15’s physical lane number.
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Opcode field[7:0] | 0x49: Get Test status 0x0D: Get PMA status |
0x42 | 0x0F
Note: 0x0F is not equivalent to 0xF
|
|
0x41 |
proc attribute_access {{data field} {option field} {lane number field} {opcode field}}You can use any programming language to perform the read and writes. For the other FGT PMA lanes, refer to FGT Attribute Access Addresses for JTAG Master that Controls 16 channels for LINK_MNG_SIDE_CPI_REGS and PHY_SIDE_CPI_REGS, and refer to FGT Attribute Access Data Value 1 for lane number field information.