Visible to Intel only — GUID: odk1614284547530
Ixiasoft
Visible to Intel only — GUID: odk1614284547530
Ixiasoft
4.1. IP Parameters
Parameter | Values | Description |
---|---|---|
System PLL #0 | ||
Mode of system PLL | Disabled | Selects the mode of system PLL #0.
|
User configuration | ||
User PCIe-based configuration | ||
ETHERNET_FREQ_805_156 | ||
ETHERNET_FREQ_805_312 | ||
ETHERNET_FREQ_805_322 41. | ||
ETHERNET_FREQ_830_156 | ||
ETHERNET_FREQ_830_312 | ||
PCIE_FREQ_1000 | ||
PCIE_FREQ_500 | ||
PCIE_FREQ_550 | ||
PCIE_FREQ_600 | ||
PCIE_FREQ_650 | ||
PCIE_FREQ_700 | ||
PCIE_FREQ_750 | ||
PCIE_FREQ_800 | ||
PCIE_FREQ_850 | ||
PCIE_FREQ_900 | ||
PCIE_FREQ_950 | ||
Refclk source | Refclk #0 | Selects the logical reference clock source for system PLL #0. The reference clock source can be shared with FGT PMA and other system PLLs. The default value is Refclk #0. |
Refclk #1 | ||
Refclk #2 | ||
Refclk #3 | ||
Refclk #4 | ||
Refclk #5 | ||
Refclk #6 | ||
Refclk #7 | ||
Refclk #8 | ||
Refclk #9 | ||
Output frequency | 31.25 to 1000 MHz | Specifies the output frequency of the system PLL #0 in MHz. In background, the algorithm calculates the legal reference clock frequencies for that clock output frequency. For correct calculation, specify the exact frequency with decimal points. The default value is 805.6640625. |
System PLL #1 | ||
Mode of system PLL | Disabled | Selects the mode of system PLL #1.
|
User configuration | ||
User PCIE-based configuration | ||
ETHERNET_FREQ_805_156 | ||
ETHERNET_FREQ_805_312 | ||
ETHERNET_FREQ_805_322 41. | ||
ETHERNET_FREQ_830_156 | ||
ETHERNET_FREQ_830_312 | ||
ETHERNET_FREQ_830_312 | ||
PCIE_FREQ_1000 | ||
PCIE_FREQ_500 | ||
PCIE_FREQ_550 | ||
PCIE_FREQ_600 | ||
PCIE_FREQ_650 | ||
PCIE_FREQ_700 | ||
PCIE_FREQ_750 | ||
PCIE_FREQ_800 | ||
PCIE_FREQ_850 | ||
PCIE_FREQ_900 | ||
PCIE_FREQ_950 | ||
Refclk source | Refclk #0 | Selects the logical reference clock source for system PLL #1. The reference clock source can be shared with FGT PMA and other system PLLs. |
Refclk #1 | ||
Refclk #2 | ||
Refclk #3 | ||
Refclk #4 | ||
Refclk #5 | ||
Refclk #6 | ||
Refclk #7 | ||
Refclk #8 | ||
Refclk #9 | ||
Output frequency | 31.25 to 1000 MHz | Specifies the output frequency of the system PLL #1 in MHz. In background, the algorithm calculates the legal reference clock frequencies for that clock output frequency. For correct calculation, must specify the exact frequency with decimal points. |
System PLL #2 | ||
Mode of system PLL | Disabled | Selects the mode of system PLL #2.
|
User configuration | ||
User PCIE-based configuration | ||
ETHERNET_FREQ_805_156 | ||
ETHERNET_FREQ_805_312 | ||
ETHERNET_FREQ_805_322 41. | ||
ETHERNET_FREQ_830_156 | ||
ETHERNET_FREQ_830_312 | ||
ETHERNET_FREQ_830_312 | ||
PCIE_FREQ_1000 | ||
PCIE_FREQ_500 | ||
PCIE_FREQ_550 | ||
PCIE_FREQ_600 | ||
PCIE_FREQ_650 | ||
PCIE_FREQ_700 | ||
PCIE_FREQ_750 | ||
PCIE_FREQ_800 | ||
PCIE_FREQ_850 | ||
PCIE_FREQ_900 | ||
PCIE_FREQ_950 | ||
Refclk source | Refclk #0 | Selects the logical reference clock source for system PLL #2. The reference clock source can be shared with FGT PMA and other system PLLs. |
Refclk #1 | ||
Refclk #2 | ||
Refclk #3 | ||
Refclk #4 | ||
Refclk #5 | ||
Refclk #6 | ||
Refclk #7 | ||
Refclk #8 | ||
Refclk #9 | ||
Output Frequency | 31.25 to 1000 MHz | Specifies the output frequency of the system PLL #2 in MHz. In background, the algorithm calculates the legal reference clock frequencies for that clock output frequency. For correct calculation, must specify the exact frequency with decimal points. |
FHT Common PLL | ||
Controller source | Auto, CommonPLL A, CommonPLL B | If both common PLLs are enabled, this selection specifies the common PLL that drives the FHT microcontroller. The reference clock that drives this common PLL must be present and stable throughout F-tile operation. |
FHT Common PLL A | ||
Enable FHT Common PLL A | On/Off | Enable/Disable FHT common PLL A. When enabled, must provide FHT reference clock source and frequency. The default value is Off. |
FHT refclk source | FHT Refclk #0 | Specifies the logical reference clock source for FHT common PLL A. The default value is FHT Refclk #0. |
FHT Refclk #1 | ||
FHT Common PLL B | ||
Enable FHT Common PLL B | On/Off | When enabled, must provide FHT reference clock source and frequency. The default value is Off. |
FHT refclk source | FHT Refclk #0 | Specifies the logical reference clock source for FHT common PLL B. The default value is FHT Refclk #0. |
FHT Refclk #1 | ||
Reference clock(s) | ||
FGT/System PLL | ||
Enable Refclk #0 for FGT PMA | On/Off | Enables logical reference clock #0 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off. |
Refclk frequency #0 | 25 to 380 MHz | Specifies the reference clock #0 frequency. Range is:
|
Refclk #0 is active at and after device configuration | On/Off | When On, you must provide the reference clock #0 which is free running and stable at and after device programming time. When Off, the reference clock can be inactive at device programming time, or can go down during device operation. Special handling of en_refclk_fgt_0 signal is required. The default value is On. |
Export Refclk #0 for use in user logic | On/Off | Allow FGT reference clock #0 to be used in user logic. The default value is Off. |
Enable Refclk #1 for FGT PMA | On/Off | Enables logical reference clock #1 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off. |
Refclk frequency #1 | 25 to 380 MHz | Specifies the reference clock #1 frequency. Range is:
|
Refclk #1 is active at and after device configuration | On/Off | When On, you must provide the reference clock #1 which is free running and stable at and after device programming time. When Off, the reference clock can be inactive at device programming time, or can go down during device operation. Special handling of en_refclk_fgt_1 signal is required. The default value is On. |
Export Refclk #1 for use in user logic | On/Off | Allow FGT reference clock #1 to be used in user logic. The default value is Off. |
Enable Refclk #2 for FGT PMA | On/Off | Enable logical reference clock #2 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off. |
Refclk frequency #2 | 25 to 380 MHz | Specifies the reference clock #2 frequency. Range is:
|
Refclk #2 is active at and after device configuration | On/Off | When On, you must provide the reference clock #2 which is free running and stable at and after device programming time. When Off, the reference clock can be inactive at device programming time, or can go down during device operation. Special handling of en_refclk_fgt_2 signal is required. The default value is On. |
Export Refclk #2 for use in user logic | On/Off | Allow FGT reference clock #2 to be used in user logic. The default value is Off. |
Enable Refclk #3 for FGT PMA | On/Off | Enable logical reference clock #3 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off. |
Refclk frequency #3 | 25 to 380 MHz | Specifies the reference clock #3 frequency. Range is:
|
Refclk #3 is active at and after device configuration | On/Off | When On, you must provide the reference clock #3 which is free running and stable at and after device programming time. When Off, the reference clock can be inactive at device programming time, or can go down during device operation. Special handling of en_refclk_fgt_3 signal is required. The default value is On. |
Export Refclk #3 for use in user logic | On/Off | Allow FGT reference clock #3 to be used in user logic. The default value is Off. |
Enable Refclk #4 for FGT PMA | On/Off | Enable logical reference clock #4 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off. |
Refclk frequency #4 | 25 to 380 MHz | Specifies the reference clock #4 frequency. Range is:
|
Refclk #4 is active at and after device configuration | On/Off | When On, you must provide the reference clock #4 which is free running and stable at and after device programming time. When Off, the reference clock can be inactive at device programming time, or can go down during device operation. Special handling of en_refclk_fgt_4 signal is required. The default value is On. |
Export Refclk #4 for use in user logic | On/Off | Allow FGT reference clock #4 to be used in user logic. The default value is Off. |
Enable Refclk #5 for FGT PMA | On/Off | Enable logical reference clock #5 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off. |
Refclk frequency #5 | 25 to 380 MHz | Specifies the reference clock #5 frequency. Range is:
|
Refclk #5 is active at and after device configuration | On/Off | When On, you must provide the reference clock #5 which is free running and stable at and after device programming time. When Off, the reference clock can be inactive at device programming time, or can go down during device operation. Special handling of en_refclk_fgt_5 signal is required. The default value is On. |
Export Refclk #5 for use in user logic | On/Off | Allow FGT reference clock #5 to be used in user logic. The default value is Off. |
Enable Refclk #6 for FGT PMA | On/Off | Enable logical reference clock #6 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off. |
Refclk frequency #6 | 25 to 380 MHz | Specifies the reference clock #6 frequency. Range is:
|
Refclk #6 is active at and after device configuration | On/Off | When On, you must provide the reference clock #6 which is free running and stable at and after device programming time. When Off, the reference clock can be inactive at device programming time, or can go down during device operation. Special handling of en_refclk_fgt_6 signal is required. The default value is On. |
Export Refclk #6 for use in user logic | On/Off | Allow FGT reference clock #6 to be used in user logic. The default value is Off. |
Enable Refclk #7 for FGT PMA | On/Off | Enable logical reference clock #7 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off. |
Refclk frequency #7 | 25 to 380 MHz | Specifies the reference clock #7 frequency. Range is:
|
Refclk #7 is active at and after device configuration | On/Off | When On, you must provide the reference clock #7 which is free running and stable at and after device programming time. When Off, the reference clock can be inactive at device programming time, or can go down during device operation. Special handling of en_refclk_fgt_7 signal is required. The default value is On. |
Export Refclk #7 for use in user logic | On/Off | Allow FGT reference clock #7 to be used in user logic. The default value is Off. |
Enable Refclk #8 for FGT PMA | On/Off | Enable logical reference clock #8 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off. |
Refclk frequency #8 | 25 to 380 MHz | Specifies the reference clock #8 frequency. Range is:
|
Refclk #8 is active at and after device configuration | On/Off | When On, you must provide the reference clock #8 which is free running and stable at and after device programming time. When Off, the reference clock can be inactive at device programming time, or can go down during device operation. Special handling of en_refclk_fgt_8 signal is required. The default value is On. |
Export Refclk #8 for use in user logic | On/Off | Allow FGT reference clock #8 to be used in user logic. The default value is Off. |
Enable Refclk #9 for FGT PMA | On/Off | Enable logical reference clock #9 for FGT PMA. This reference clock can also be shared by system PLL. The default value is Off. |
Refclk frequency #9 | 25 to 380 MHz | Specifies the reference clock #9 frequency. Range is:
|
Refclk #9 is active at and after device configuration | On/Off | When On, you must provide the reference clock #9 which is free running and stable at and after device programming time. When Off, the reference clock can be inactive at device programming time, or can go down during device operation. Special handling of en_refclk_fgt_9 signal is required. The default value is On. |
Export Refclk #9 for use in user logic | On/Off | Allow FGT reference clock #9 to be used in user logic. The default value is Off. |
FGT CDR Clock-out(s) | ||
Enable FGT CDR Output #0 | On/Off | Enables logical FGT CDR clock output #0. This must be enabled to configure FGT reference clock as a CDR clock output. The default value is Off. |
Enable FGT CDR Output #1 | On/Off | Enables logical FGT CDR clock output #1. This must be enabled to configure FGT reference clock as a CDR clock output. The default value is Off. |
FHT Reference clock(s) | ||
FHT Refclk frequency #0 | 100 to 200 MHz | Specifies the FHT reference clock #0 frequency in MHz. |
FHT Refclk frequency #1 | 100 to 200 MHz | Specifies the FHT reference clock #1 frequency in MHz. |