F-tile Architecture and PMA and FEC Direct PHY IP User Guide
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Visible to Intel only — GUID: ubp1678309340915
Ixiasoft
Visible to Intel only — GUID: ubp1678309340915
Ixiasoft
3.11.6.3. Accessing FGT PMA Registers
- For the channel on lane 0: offset address + channel base address
- For the channel on lane 1: offset address + 0x8000 + channel base address
- For the channel on lane 2: offset address + 0x10000 + channel base address
- For the channel on lane 3: offset address + 0x18000 + channel base address
- For channels 0, 1, 2 or 3: 0x000000
- For channels 4, 5, 6 or 7: 0x400000
- For channels 8, 9, 10 or 11: 0x800000
- For channels 12, 13, 14 or 15: 0xC00000
FGT PMA Register Access Example 1
- Channel 0 is placed on Quad 3, Lane 3
- Channel 1 is placed on Quad 3, Lane 2
- Channel 2 is placed on Quad 3, Lane 1
- Channel 3 is placed on Quad 3, Lane 0
- Channel 4 is placed on Quad 2, Lane 3
- Channel 5 is placed on Quad 2, Lane 2
- Channel 6 is placed on Quad 2, Lane 1
- Channel 7 is placed on Quad 2, Lane 0
- Channel 8 is placed on Quad 1, Lane 3
- Channel 9 is placed on Quad 1, Lane 2
- Channel 0: 0x5f830 (0x47830 + 0x18000 + 0x000000)
- Channel 1: 0x57830 (0x47830 + 0x10000 + 0x000000)
- Channel 2: 0x4f830 (0x47830 + 0x8000 + 0x000000)
- Channel 3: 0x47830 (0x47830 + 0x000000)
- Channel 4: 0x45f830 (0x47830 + 0x18000 + 0x400000)
- Channel 5: 0x457830 (0x47830 + 0x10000 + 0x400000)
- Channel 6: 0x44f830 (0x47830 + 0x8000 + 0x400000)
- Channel 7: 0x447830 (0x47830 + 0x400000)
- Channel 8: 0x85f830 (0x47830 + 0x18000 + 0x800000)
- Channel 9: 0x857830 (0x47830 + 0x10000 + 0x800000)
- For channels 0, 1, 2 or 3: offset address + 0x000000
- For channels 4, 5, 6 or 7: offset address + 0x400000
- For channels 8, 9, 10 or 11: offset address + 0x800000
- For channels 12, 13, 14 or 15: offset address + 0xC00000
For FGT PMA registers with offset address as 0x62000, 0x62004, or 0x62008, you must directly use the offset address provided in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP register map.
For FGT PMA registers with offset address greater than 0xF0000 and less than 0xFFFFC, you must directly use the offset address provided in theF-Tile PMA/FEC Direct PHY Intel® FPGA IP register map.
- For channel 0: 0xFFFFC
- For channel 1: 0x1FFFFC
- For channel 2: 0x2FFFFC
- For channel 3: 0x3FFFFC
- For channel 4: 0x4FFFFC
- For channel 5: 0x5FFFFC
- For channel 6: 0x6FFFFC
- For channel 7: 0x7FFFFC
- For channel 8: 0x8FFFFC
- For channel 9: 0x9FFFFC
- For channel 10: 0xAFFFFC
- For channel 11: 0xBFFFFC
- For channel 12: 0xCFFFFC
- For channel 13: 0xDFFFFC
- For channel 14: 0xEFFFFC
- For channel 15: 0xFFFFFC