1. F-tile Overview
|Intel® Quartus® Prime Design Suite 23.2|
|IP Version 4.5.0|
F-tile is a PAM4 and NRZ dual-mode serial interface tile that contains 16 FGT PMAs and four FHT PMAs. F-tile contains multiple hard IP blocks for use in conjunction with the PMAs to allow efficient implementation of popular and emerging serial protocols. F-tile connects to the FPGA fabric using the Intel embedded multi-die interconnect bridge (EMIB) technology.
|Number of available PMAs||Up to 20.
Not all FHT PMAs bond out in every tile. Refer to Intel® Agilex™ 7 Device Family Pin Connection Guidelines .
|Data rate range||FHT:
Not all FGT PMAs support the same data rates. Refer to PMA Data Rates.
|Number of EMIBs||24|
|PCIe* hard IP modes||Up to one Gen4 x16, two Gen4 x8, or four Gen4 x4.|
|Ethernet hard IP modes with number of supported PMAs for each, where 10GbE-1 is 10GbE mode supporting one PMA||
10GbE-1, 25GbE-1, 40GbE-4, 50GbE-2, 50GbE-1, 100GbE-4, 100GbE-2, 100GbE-1, 200GbE-8, 200GbE-4, 200GbE-2, 400GbE-8, and 400GbE-4, with these optional features:
Includes Ethernet PCS and MAC for all data rates. Not all features are supported for all data rates. Refer to F-Tile Ethernet Intel FPGA Hard IP User Guide.
|Forward error correction (FEC) and Reed-Solomon FEC (RS-FEC) modes||
Refer to F-Tile Supported FEC Modes and Compliance Specifications.
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