3.11.5. Lane Offset Address
Lane offset address information is the offset for each lane in the FHT and FGT PMA Register Maps.
The following table shows the FHT PMA lane number to offset address mapping. Word address is byte address/4.
|Lane Number||Lane Base Offset Address (Byte address)|
For example, if you want to control the RX loopback and polarity inversion, refer to the SERDES_LANE_LANE_CTRL_LANE_RX_CTRL register for lane 0 (0x45800) in the register map file and add 0x8000h for each incremental lane, as shown below:
- Lane0 → 0x45800
- Lane1 → 0x4D800
- Lane2 → 0x55800
- Lane3 → 0x5D800
The following table shows the FGT PMA offset address for each lane within a quad. Word address is byte address/4.
|Lane Number||Lane Base Offset Address (Byte Address)|
- Lane0 → 0x47830
- Lane1 → 0x4F830
- Lane2 → 0x57830
- Lane3 → 0x5F830